2802 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2867 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2868 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2871 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2873 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2892 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2893 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2902 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2903 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2911 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2913 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2926 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2927 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2930 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2932 							src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2972 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
2973 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2974 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2976 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3012 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3013 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3014 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3016 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3074 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3075 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3076 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3078 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3103 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3104 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3113 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3114 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3122 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3124 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3161 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3162 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3163 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3165 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()