Lines Matching refs:psr
99 if (dev_priv->psr.psr2_support) { in hsw_psr_setup_vsc()
104 if (dev_priv->psr.colorimetry_support && in hsw_psr_setup_vsc()
105 dev_priv->psr.y_cord_support) { in hsw_psr_setup_vsc()
108 } else if (dev_priv->psr.y_cord_support) { in hsw_psr_setup_vsc()
175 if (dev_priv->psr.aux_frame_sync) in hsw_psr_enable_sink()
180 if (dev_priv->psr.psr2_support && dev_priv->psr.alpm) in hsw_psr_enable_sink()
184 if (dev_priv->psr.link_standby) in hsw_psr_enable_sink()
249 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); in hsw_activate_psr1()
258 if (dev_priv->psr.link_standby) in hsw_activate_psr1()
261 if (dev_priv->vbt.psr.tp1_wakeup_time > 5) in hsw_activate_psr1()
263 else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) in hsw_activate_psr1()
265 else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) in hsw_activate_psr1()
270 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) in hsw_activate_psr1()
272 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) in hsw_activate_psr1()
274 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) in hsw_activate_psr1()
301 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); in hsw_activate_psr2()
322 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) in hsw_activate_psr2()
324 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) in hsw_activate_psr2()
326 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) in hsw_activate_psr2()
346 if (dev_priv->psr.psr2_support) in hsw_psr_activate()
385 !dev_priv->psr.link_standby) { in intel_psr_compute_config()
422 if (!dev_priv->psr.psr2_support) { in intel_psr_compute_config()
438 if (!dev_priv->psr.y_cord_support) { in intel_psr_compute_config()
453 if (dev_priv->psr.psr2_support) in intel_psr_activate()
457 WARN_ON(dev_priv->psr.active); in intel_psr_activate()
458 lockdep_assert_held(&dev_priv->psr.lock); in intel_psr_activate()
460 dev_priv->psr.activate(intel_dp); in intel_psr_activate()
461 dev_priv->psr.active = true; in intel_psr_activate()
473 if (dev_priv->psr.psr2_support) { in hsw_psr_enable_source()
475 if (dev_priv->psr.y_cord_support) in hsw_psr_enable_source()
518 mutex_lock(&dev_priv->psr.lock); in intel_psr_enable()
519 if (dev_priv->psr.enabled) { in intel_psr_enable()
524 dev_priv->psr.psr2_support = crtc_state->has_psr2; in intel_psr_enable()
525 dev_priv->psr.source_ok = true; in intel_psr_enable()
527 dev_priv->psr.busy_frontbuffer_bits = 0; in intel_psr_enable()
529 dev_priv->psr.setup_vsc(intel_dp, crtc_state); in intel_psr_enable()
530 dev_priv->psr.enable_sink(intel_dp); in intel_psr_enable()
531 dev_priv->psr.enable_source(intel_dp, crtc_state); in intel_psr_enable()
532 dev_priv->psr.enabled = intel_dp; in intel_psr_enable()
547 schedule_delayed_work(&dev_priv->psr.work, in intel_psr_enable()
552 mutex_unlock(&dev_priv->psr.lock); in intel_psr_enable()
564 if (dev_priv->psr.active) { in vlv_psr_disable()
579 dev_priv->psr.active = false; in vlv_psr_disable()
592 if (dev_priv->psr.active) { in hsw_psr_disable()
596 if (dev_priv->psr.aux_frame_sync) in hsw_psr_disable()
601 if (dev_priv->psr.psr2_support) { in hsw_psr_disable()
623 dev_priv->psr.active = false; in hsw_psr_disable()
625 if (dev_priv->psr.psr2_support) in hsw_psr_disable()
649 mutex_lock(&dev_priv->psr.lock); in intel_psr_disable()
650 if (!dev_priv->psr.enabled) { in intel_psr_disable()
651 mutex_unlock(&dev_priv->psr.lock); in intel_psr_disable()
655 dev_priv->psr.disable_source(intel_dp, old_crtc_state); in intel_psr_disable()
660 dev_priv->psr.enabled = NULL; in intel_psr_disable()
661 mutex_unlock(&dev_priv->psr.lock); in intel_psr_disable()
663 cancel_delayed_work_sync(&dev_priv->psr.work); in intel_psr_disable()
669 container_of(work, typeof(*dev_priv), psr.work.work); in intel_psr_work()
670 struct intel_dp *intel_dp = dev_priv->psr.enabled; in intel_psr_work()
680 if (dev_priv->psr.psr2_support) { in intel_psr_work()
709 mutex_lock(&dev_priv->psr.lock); in intel_psr_work()
710 intel_dp = dev_priv->psr.enabled; in intel_psr_work()
720 if (dev_priv->psr.busy_frontbuffer_bits) in intel_psr_work()
725 mutex_unlock(&dev_priv->psr.lock); in intel_psr_work()
730 struct intel_dp *intel_dp = dev_priv->psr.enabled; in intel_psr_exit()
735 if (!dev_priv->psr.active) in intel_psr_exit()
739 if (dev_priv->psr.aux_frame_sync) in intel_psr_exit()
743 if (dev_priv->psr.psr2_support) { in intel_psr_exit()
779 dev_priv->psr.active = false; in intel_psr_exit()
809 mutex_lock(&dev_priv->psr.lock); in intel_psr_single_frame_update()
810 if (!dev_priv->psr.enabled) { in intel_psr_single_frame_update()
811 mutex_unlock(&dev_priv->psr.lock); in intel_psr_single_frame_update()
815 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; in intel_psr_single_frame_update()
827 mutex_unlock(&dev_priv->psr.lock); in intel_psr_single_frame_update()
851 mutex_lock(&dev_priv->psr.lock); in intel_psr_invalidate()
852 if (!dev_priv->psr.enabled) { in intel_psr_invalidate()
853 mutex_unlock(&dev_priv->psr.lock); in intel_psr_invalidate()
857 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; in intel_psr_invalidate()
861 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; in intel_psr_invalidate()
866 mutex_unlock(&dev_priv->psr.lock); in intel_psr_invalidate()
891 mutex_lock(&dev_priv->psr.lock); in intel_psr_flush()
892 if (!dev_priv->psr.enabled) { in intel_psr_flush()
893 mutex_unlock(&dev_priv->psr.lock); in intel_psr_flush()
897 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; in intel_psr_flush()
901 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; in intel_psr_flush()
907 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) in intel_psr_flush()
908 if (!work_busy(&dev_priv->psr.work.work)) in intel_psr_flush()
909 schedule_delayed_work(&dev_priv->psr.work, in intel_psr_flush()
911 mutex_unlock(&dev_priv->psr.lock); in intel_psr_flush()
936 dev_priv->psr.link_standby = false; in intel_psr_init()
939 dev_priv->psr.link_standby = true; in intel_psr_init()
942 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; in intel_psr_init()
945 if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) { in intel_psr_init()
947 dev_priv->psr.link_standby = true; in intel_psr_init()
949 if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) { in intel_psr_init()
951 dev_priv->psr.link_standby = false; in intel_psr_init()
954 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); in intel_psr_init()
955 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE); in intel_psr_init()
958 dev_priv->psr.enable_source = vlv_psr_enable_source; in intel_psr_init()
959 dev_priv->psr.disable_source = vlv_psr_disable; in intel_psr_init()
960 dev_priv->psr.enable_sink = vlv_psr_enable_sink; in intel_psr_init()
961 dev_priv->psr.activate = vlv_psr_activate; in intel_psr_init()
962 dev_priv->psr.setup_vsc = vlv_psr_setup_vsc; in intel_psr_init()
964 dev_priv->psr.enable_source = hsw_psr_enable_source; in intel_psr_init()
965 dev_priv->psr.disable_source = hsw_psr_disable; in intel_psr_init()
966 dev_priv->psr.enable_sink = hsw_psr_enable_sink; in intel_psr_init()
967 dev_priv->psr.activate = hsw_psr_activate; in intel_psr_init()
968 dev_priv->psr.setup_vsc = hsw_psr_setup_vsc; in intel_psr_init()