951 struct intel_dp {  struct
952 	i915_reg_t output_reg;
953 	i915_reg_t aux_ch_ctl_reg;
954 	i915_reg_t aux_ch_data_reg[5];
955 	uint32_t DP;
956 	int link_rate;
957 	uint8_t lane_count;
958 	uint8_t sink_count;
959 	bool link_mst;
960 	bool has_audio;
961 	bool detect_done;
962 	bool channel_eq_status;
963 	bool reset_link_params;
964 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
965 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
966 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
967 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
969 	int num_source_rates;
970 	const int *source_rates;
972 	int num_sink_rates;
973 	int sink_rates[DP_MAX_SUPPORTED_RATES];
974 	bool use_rate_select;
976 	int num_common_rates;
977 	int common_rates[DP_MAX_SUPPORTED_RATES];
979 	int max_link_lane_count;
981 	int max_link_rate;
983 	struct drm_dp_desc desc;
984 	struct drm_dp_aux aux;
985 	enum intel_display_power_domain aux_power_domain;
986 	uint8_t train_set[4];
987 	int panel_power_up_delay;
988 	int panel_power_down_delay;
989 	int panel_power_cycle_delay;
990 	int backlight_on_delay;
991 	int backlight_off_delay;
992 	struct delayed_work panel_vdd_work;
993 	bool want_panel_vdd;
994 	unsigned long last_power_on;
995 	unsigned long last_backlight_off;
996 	ktime_t panel_power_off_time;
998 	struct notifier_block edp_notifier;
1025 	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];  argument
1028 	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);  argument
1033 	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,  argument
1039 	void (*prepare_link_retrain)(struct intel_dp *intel_dp);  argument
1042 	struct intel_dp_compliance compliance;  argument
1175 dp_to_dig_port(struct intel_dp *intel_dp)  in dp_to_dig_port()
1181 dp_to_lspcon(struct intel_dp *intel_dp)  in dp_to_lspcon()