Lines Matching refs:plane
1241 static void assert_plane(struct intel_plane *plane, bool state) in assert_plane() argument
1243 bool cur_state = plane->get_hw_state(plane); in assert_plane()
1247 plane->base.name, onoff(state), onoff(cur_state)); in assert_plane()
1256 struct intel_plane *plane; in assert_planes_disabled() local
1258 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in assert_planes_disabled()
1259 assert_plane_disabled(plane); in assert_planes_disabled()
1950 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) in intel_tile_width_bytes() argument
1953 unsigned int cpp = fb->format->cpp[plane]; in intel_tile_width_bytes()
1964 if (plane == 1) in intel_tile_width_bytes()
1973 if (plane == 1) in intel_tile_width_bytes()
1998 intel_tile_height(const struct drm_framebuffer *fb, int plane) in intel_tile_height() argument
2004 intel_tile_width_bytes(fb, plane); in intel_tile_height()
2008 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, in intel_tile_dims() argument
2012 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); in intel_tile_dims()
2013 unsigned int cpp = fb->format->cpp[plane]; in intel_tile_dims()
2021 int plane, unsigned int height) in intel_fb_align_height() argument
2023 unsigned int tile_height = intel_tile_height(fb, plane); in intel_fb_align_height()
2033 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) in intel_rotation_info_size()
2034 size += rot_info->plane[i].width * rot_info->plane[i].height; in intel_rotation_info_size()
2077 int plane) in intel_surf_alignment() argument
2082 if (plane == 1) in intel_surf_alignment()
2179 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, in intel_fb_pitch() argument
2183 return to_intel_framebuffer(fb)->rotated[plane].pitch; in intel_fb_pitch()
2185 return fb->pitches[plane]; in intel_fb_pitch()
2196 int plane) in intel_fb_xy_to_linear() argument
2199 unsigned int cpp = fb->format->cpp[plane]; in intel_fb_xy_to_linear()
2200 unsigned int pitch = fb->pitches[plane]; in intel_fb_xy_to_linear()
2212 int plane) in intel_add_fb_offsets() argument
2219 *x += intel_fb->rotated[plane].x; in intel_add_fb_offsets()
2220 *y += intel_fb->rotated[plane].y; in intel_add_fb_offsets()
2222 *x += intel_fb->normal[plane].x; in intel_add_fb_offsets()
2223 *y += intel_fb->normal[plane].y; in intel_add_fb_offsets()
2255 const struct drm_framebuffer *fb, int plane, in _intel_adjust_tile_offset() argument
2260 unsigned int cpp = fb->format->cpp[plane]; in _intel_adjust_tile_offset()
2261 unsigned int pitch = intel_fb_pitch(fb, plane, rotation); in _intel_adjust_tile_offset()
2270 intel_tile_dims(fb, plane, &tile_width, &tile_height); in _intel_adjust_tile_offset()
2297 const struct intel_plane_state *state, int plane, in intel_adjust_tile_offset() argument
2300 return _intel_adjust_tile_offset(x, y, state->base.fb, plane, in intel_adjust_tile_offset()
2321 const struct drm_framebuffer *fb, int plane, in _intel_compute_tile_offset() argument
2327 unsigned int cpp = fb->format->cpp[plane]; in _intel_compute_tile_offset()
2338 intel_tile_dims(fb, plane, &tile_width, &tile_height); in _intel_compute_tile_offset()
2372 int plane) in intel_compute_tile_offset() argument
2374 struct intel_plane *intel_plane = to_intel_plane(state->base.plane); in intel_compute_tile_offset()
2378 int pitch = intel_fb_pitch(fb, plane, rotation); in intel_compute_tile_offset()
2384 alignment = intel_surf_alignment(fb, plane); in intel_compute_tile_offset()
2386 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, in intel_compute_tile_offset()
2392 const struct drm_framebuffer *fb, int plane) in intel_fb_offset_to_xy() argument
2397 fb->offsets[plane] % intel_tile_size(dev_priv)) in intel_fb_offset_to_xy()
2404 fb, plane, DRM_MODE_ROTATE_0, in intel_fb_offset_to_xy()
2405 fb->offsets[plane], 0); in intel_fb_offset_to_xy()
2554 rot_info->plane[i].offset = offset; in intel_fill_fb_info()
2555 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); in intel_fill_fb_info()
2556 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); in intel_fill_fb_info()
2557 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); in intel_fill_fb_info()
2560 rot_info->plane[i].height * tile_height; in intel_fill_fb_info()
2563 size = rot_info->plane[i].stride * rot_info->plane[i].height; in intel_fill_fb_info()
2577 rot_info->plane[i].width * tile_width, in intel_fill_fb_info()
2578 rot_info->plane[i].height * tile_height, in intel_fill_fb_info()
2596 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; in intel_fill_fb_info()
2732 struct intel_plane *plane = to_intel_plane(plane_state->base.plane); in intel_set_plane_visible() local
2738 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); in intel_set_plane_visible()
2739 crtc_state->active_planes |= BIT(plane->id); in intel_set_plane_visible()
2741 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); in intel_set_plane_visible()
2742 crtc_state->active_planes &= ~BIT(plane->id); in intel_set_plane_visible()
2751 struct intel_plane *plane) in intel_plane_disable_noatomic() argument
2756 to_intel_plane_state(plane->base.state); in intel_plane_disable_noatomic()
2760 if (plane->id == PLANE_PRIMARY) in intel_plane_disable_noatomic()
2763 trace_intel_disable_plane(&plane->base, crtc); in intel_plane_disable_noatomic()
2764 plane->disable_plane(plane, crtc); in intel_plane_disable_noatomic()
2871 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, in skl_max_plane_width() argument
2874 int cpp = fb->format->cpp[plane]; in skl_max_plane_width()
3063 struct intel_plane *plane = to_intel_plane(plane_state->base.plane); in skl_check_ccs_aux_surface() local
3074 switch (plane->id) { in skl_check_ccs_aux_surface()
3149 to_i915(plane_state->base.plane->dev); in i9xx_plane_ctl()
3210 to_i915(plane_state->base.plane->dev); in i9xx_check_plane_surface()
3250 enum plane plane = primary->plane; in i9xx_update_primary_plane() local
3253 i915_reg_t reg = DSPCNTR(plane); in i9xx_update_primary_plane()
3272 I915_WRITE_FW(DSPSIZE(plane), in i9xx_update_primary_plane()
3275 I915_WRITE_FW(DSPPOS(plane), 0); in i9xx_update_primary_plane()
3276 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { in i9xx_update_primary_plane()
3277 I915_WRITE_FW(PRIMSIZE(plane), in i9xx_update_primary_plane()
3280 I915_WRITE_FW(PRIMPOS(plane), 0); in i9xx_update_primary_plane()
3281 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); in i9xx_update_primary_plane()
3286 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); in i9xx_update_primary_plane()
3288 I915_WRITE_FW(DSPSURF(plane), in i9xx_update_primary_plane()
3291 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); in i9xx_update_primary_plane()
3293 I915_WRITE_FW(DSPSURF(plane), in i9xx_update_primary_plane()
3296 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); in i9xx_update_primary_plane()
3297 I915_WRITE_FW(DSPLINOFF(plane), linear_offset); in i9xx_update_primary_plane()
3299 I915_WRITE_FW(DSPADDR(plane), in i9xx_update_primary_plane()
3312 enum plane plane = primary->plane; in i9xx_disable_primary_plane() local
3317 I915_WRITE_FW(DSPCNTR(plane), 0); in i9xx_disable_primary_plane()
3319 I915_WRITE_FW(DSPSURF(plane), 0); in i9xx_disable_primary_plane()
3321 I915_WRITE_FW(DSPADDR(plane), 0); in i9xx_disable_primary_plane()
3322 POSTING_READ_FW(DSPCNTR(plane)); in i9xx_disable_primary_plane()
3332 enum plane plane = primary->plane; in i9xx_plane_get_hw_state() local
3345 ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE; in i9xx_plane_get_hw_state()
3353 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) in intel_fb_stride_alignment() argument
3358 return intel_tile_width_bytes(fb, plane); in intel_fb_stride_alignment()
3388 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, in skl_plane_stride() argument
3393 if (plane >= fb->format->num_planes) in skl_plane_stride()
3396 stride = intel_fb_pitch(fb, plane, rotation); in skl_plane_stride()
3403 stride /= intel_tile_height(fb, plane); in skl_plane_stride()
3405 stride /= intel_fb_stride_alignment(fb, plane); in skl_plane_stride()
3499 to_i915(plane_state->base.plane->dev); in skl_plane_ctl()
4719 to_intel_plane(plane_state->base.plane); in skl_update_scaler_plane()
5868 struct intel_plane *plane; in intel_crtc_disable_noatomic() local
5877 for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) { in intel_crtc_disable_noatomic()
5879 to_intel_plane_state(plane->base.state); in intel_crtc_disable_noatomic()
5882 intel_plane_disable_noatomic(intel_crtc, plane); in intel_crtc_disable_noatomic()
7392 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config() local
7398 val = I915_READ(DSPCNTR(plane)); in i9xx_get_initial_plane_config()
7425 offset = I915_READ(DSPTILEOFF(plane)); in i9xx_get_initial_plane_config()
7427 offset = I915_READ(DSPLINOFF(plane)); in i9xx_get_initial_plane_config()
7428 base = I915_READ(DSPSURF(plane)) & 0xfffff000; in i9xx_get_initial_plane_config()
7430 base = I915_READ(DSPADDR(plane)); in i9xx_get_initial_plane_config()
7446 pipe_name(pipe), plane, fb->width, fb->height, in i9xx_get_initial_plane_config()
9242 to_i915(plane_state->base.plane->dev); in intel_cursor_base()
9287 &plane_state->base.plane->dev->mode_config; in intel_cursor_size_ok()
9357 static int i845_check_cursor(struct intel_plane *plane, in i845_check_cursor() argument
9397 static void i845_update_cursor(struct intel_plane *plane, in i845_update_cursor() argument
9401 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i845_update_cursor()
9421 if (plane->cursor.base != base || in i845_update_cursor()
9422 plane->cursor.size != size || in i845_update_cursor()
9423 plane->cursor.cntl != cntl) { in i845_update_cursor()
9430 plane->cursor.base = base; in i845_update_cursor()
9431 plane->cursor.size = size; in i845_update_cursor()
9432 plane->cursor.cntl = cntl; in i845_update_cursor()
9442 static void i845_disable_cursor(struct intel_plane *plane, in i845_disable_cursor() argument
9445 i845_update_cursor(plane, NULL, NULL); in i845_disable_cursor()
9448 static bool i845_cursor_get_hw_state(struct intel_plane *plane) in i845_cursor_get_hw_state() argument
9450 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i845_cursor_get_hw_state()
9469 to_i915(plane_state->base.plane->dev); in i9xx_cursor_ctl()
9504 to_i915(plane_state->base.plane->dev); in i9xx_cursor_size_ok()
9539 static int i9xx_check_cursor(struct intel_plane *plane, in i9xx_check_cursor() argument
9543 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_check_cursor()
9545 enum i915_pipe pipe = plane->pipe; in i9xx_check_cursor()
9591 static void i9xx_update_cursor(struct intel_plane *plane, in i9xx_update_cursor() argument
9595 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_update_cursor()
9596 enum i915_pipe pipe = plane->pipe; in i9xx_update_cursor()
9630 if (plane->cursor.base != base || in i9xx_update_cursor()
9631 plane->cursor.size != fbc_ctl || in i9xx_update_cursor()
9632 plane->cursor.cntl != cntl) { in i9xx_update_cursor()
9639 plane->cursor.base = base; in i9xx_update_cursor()
9640 plane->cursor.size = fbc_ctl; in i9xx_update_cursor()
9641 plane->cursor.cntl = cntl; in i9xx_update_cursor()
9652 static void i9xx_disable_cursor(struct intel_plane *plane, in i9xx_disable_cursor() argument
9655 i9xx_update_cursor(plane, NULL, NULL); in i9xx_disable_cursor()
9658 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane) in i9xx_cursor_get_hw_state() argument
9660 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in i9xx_cursor_get_hw_state()
9662 enum i915_pipe pipe = plane->pipe; in i9xx_cursor_get_hw_state()
10227 static bool intel_wm_need_update(struct drm_plane *plane, in intel_wm_need_update() argument
10231 struct intel_plane_state *cur = to_intel_plane_state(plane->state); in intel_wm_need_update()
10269 struct intel_plane *plane = to_intel_plane(plane_state->plane); in intel_plane_atomic_calc_changes() local
10279 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
10305 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); in intel_plane_atomic_calc_changes()
10319 plane->base.base.id, plane->base.name, in intel_plane_atomic_calc_changes()
10323 plane->base.base.id, plane->base.name, in intel_plane_atomic_calc_changes()
10332 if (plane->id != PLANE_CURSOR) in intel_plane_atomic_calc_changes()
10339 if (plane->id != PLANE_CURSOR) in intel_plane_atomic_calc_changes()
10341 } else if (intel_wm_need_update(&plane->base, plane_state)) { in intel_plane_atomic_calc_changes()
10350 pipe_config->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
10358 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && in intel_plane_atomic_calc_changes()
10643 struct drm_plane *plane; in intel_dump_pipe_config() local
10713 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { in intel_dump_pipe_config()
10715 intel_plane = to_intel_plane(plane); in intel_dump_pipe_config()
10719 state = to_intel_plane_state(plane->state); in intel_dump_pipe_config()
10723 plane->base.id, plane->name, state->scaler_id); in intel_dump_pipe_config()
10728 plane->base.id, plane->name, in intel_dump_pipe_config()
11355 int plane, level, max_level = ilk_wm_max_level(dev_priv); in verify_wm_state() local
11367 for_each_universal_plane(dev_priv, pipe, plane) { in verify_wm_state()
11368 hw_plane_wm = &hw_wm.planes[plane]; in verify_wm_state()
11369 sw_plane_wm = &sw_wm->planes[plane]; in verify_wm_state()
11378 pipe_name(pipe), plane + 1, level, in verify_wm_state()
11390 pipe_name(pipe), plane + 1, in verify_wm_state()
11400 hw_ddb_entry = &hw_ddb.plane[pipe][plane]; in verify_wm_state()
11401 sw_ddb_entry = &sw_ddb->plane[pipe][plane]; in verify_wm_state()
11405 pipe_name(pipe), plane + 1, in verify_wm_state()
11450 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; in verify_wm_state()
11451 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; in verify_wm_state()
12460 struct drm_plane *plane; in intel_atomic_track_fbs() local
12463 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) in intel_atomic_track_fbs()
12466 to_intel_plane(plane)->frontbuffer_bit); in intel_atomic_track_fbs()
12644 intel_prepare_plane_fb(struct drm_plane *plane, in intel_prepare_plane_fb() argument
12649 struct drm_i915_private *dev_priv = to_i915(plane->dev); in intel_prepare_plane_fb()
12652 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); in intel_prepare_plane_fb()
12658 plane->state->crtc); in intel_prepare_plane_fb()
12703 if (plane->type == DRM_PLANE_TYPE_CURSOR && in intel_prepare_plane_fb()
12757 intel_cleanup_plane_fb(struct drm_plane *plane, in intel_cleanup_plane_fb() argument
12765 mutex_lock(&plane->dev->struct_mutex); in intel_cleanup_plane_fb()
12767 mutex_unlock(&plane->dev->struct_mutex); in intel_cleanup_plane_fb()
12805 intel_check_primary_plane(struct intel_plane *plane, in intel_check_primary_plane() argument
12809 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_check_primary_plane()
12909 void intel_plane_destroy(struct drm_plane *plane) in intel_plane_destroy() argument
12911 drm_plane_cleanup(plane); in intel_plane_destroy()
12912 kfree(to_intel_plane(plane)); in intel_plane_destroy()
12977 static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, in intel_primary_plane_format_mod_supported() argument
12981 struct drm_i915_private *dev_priv = to_i915(plane->dev); in intel_primary_plane_format_mod_supported()
13000 static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, in intel_cursor_plane_format_mod_supported() argument
13022 intel_legacy_cursor_update(struct drm_plane *plane, in intel_legacy_cursor_update() argument
13034 struct intel_plane *intel_plane = to_intel_plane(plane); in intel_legacy_cursor_update()
13047 old_plane_state = plane->state; in intel_legacy_cursor_update()
13070 new_plane_state = intel_plane_duplicate_state(plane); in intel_legacy_cursor_update()
13087 to_intel_plane_state(plane->state), in intel_legacy_cursor_update()
13122 plane->state = new_plane_state; in intel_legacy_cursor_update()
13124 if (plane->state->visible) { in intel_legacy_cursor_update()
13125 trace_intel_update_plane(plane, to_intel_crtc(crtc)); in intel_legacy_cursor_update()
13128 to_intel_plane_state(plane->state)); in intel_legacy_cursor_update()
13130 trace_intel_disable_plane(plane, to_intel_crtc(crtc)); in intel_legacy_cursor_update()
13142 intel_plane_destroy_state(plane, new_plane_state); in intel_legacy_cursor_update()
13144 intel_plane_destroy_state(plane, old_plane_state); in intel_legacy_cursor_update()
13148 return drm_atomic_helper_update_plane(plane, crtc, fb, in intel_legacy_cursor_update()
13201 primary->plane = (enum plane) !pipe; in intel_primary_plane_create()
13203 primary->plane = (enum plane) pipe; in intel_primary_plane_create()
13265 "plane %c", plane_name(primary->plane)); in intel_primary_plane_create()
13325 cursor->plane = pipe; in intel_cursor_plane_create()
13428 struct intel_plane *plane; in intel_crtc_init() local
13430 plane = intel_sprite_plane_create(dev_priv, pipe, sprite); in intel_crtc_init()
13431 if (IS_ERR(plane)) { in intel_crtc_init()
13432 ret = PTR_ERR(plane); in intel_crtc_init()
13435 intel_crtc->plane_ids_mask |= BIT(plane->id); in intel_crtc_init()
13453 intel_crtc->plane = primary->plane; in intel_crtc_init()
13459 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
13460 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; in intel_crtc_init()
14708 enum plane plane = primary->plane; in intel_plane_mapping_ok() local
14709 u32 val = I915_READ(DSPCNTR(plane)); in intel_plane_mapping_ok()
14724 struct intel_plane *plane = in intel_sanitize_plane_mapping() local
14727 if (intel_plane_mapping_ok(crtc, plane)) in intel_sanitize_plane_mapping()
14731 plane->base.name); in intel_sanitize_plane_mapping()
14732 intel_plane_disable_noatomic(crtc, plane); in intel_sanitize_plane_mapping()
14783 struct intel_plane *plane; in intel_sanitize_crtc() local
14788 for_each_intel_plane_on_crtc(dev, crtc, plane) { in intel_sanitize_crtc()
14790 to_intel_plane_state(plane->base.state); in intel_sanitize_crtc()
14793 plane->base.type != DRM_PLANE_TYPE_PRIMARY) in intel_sanitize_crtc()
14794 intel_plane_disable_noatomic(crtc, plane); in intel_sanitize_crtc()
14908 struct intel_plane *plane; in readout_plane_state() local
14910 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { in readout_plane_state()
14912 to_intel_plane_state(plane->base.state); in readout_plane_state()
14913 bool visible = plane->get_hw_state(plane); in readout_plane_state()
15362 } plane[I915_MAX_PIPES]; member
15413 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
15414 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); in intel_display_capture_error_state()
15416 error->plane[i].size = I915_READ(DSPSIZE(i)); in intel_display_capture_error_state()
15417 error->plane[i].pos = I915_READ(DSPPOS(i)); in intel_display_capture_error_state()
15420 error->plane[i].addr = I915_READ(DSPADDR(i)); in intel_display_capture_error_state()
15422 error->plane[i].surface = I915_READ(DSPSURF(i)); in intel_display_capture_error_state()
15423 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); in intel_display_capture_error_state()
15484 err_printf(m, " CNTR: %08x\n", error->plane[i].control); in intel_display_print_error_state()
15485 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); in intel_display_print_error_state()
15487 err_printf(m, " SIZE: %08x\n", error->plane[i].size); in intel_display_print_error_state()
15488 err_printf(m, " POS: %08x\n", error->plane[i].pos); in intel_display_print_error_state()
15491 err_printf(m, " ADDR: %08x\n", error->plane[i].addr); in intel_display_print_error_state()
15493 err_printf(m, " SURF: %08x\n", error->plane[i].surface); in intel_display_print_error_state()
15494 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); in intel_display_print_error_state()