160 struct vi_mqd {  struct
161 	uint32_t header;
162 	uint32_t compute_dispatch_initiator;
163 	uint32_t compute_dim_x;
164 	uint32_t compute_dim_y;
165 	uint32_t compute_dim_z;
166 	uint32_t compute_start_x;
167 	uint32_t compute_start_y;
168 	uint32_t compute_start_z;
169 	uint32_t compute_num_thread_x;
170 	uint32_t compute_num_thread_y;
171 	uint32_t compute_num_thread_z;
172 	uint32_t compute_pipelinestat_enable;
173 	uint32_t compute_perfcount_enable;
174 	uint32_t compute_pgm_lo;
175 	uint32_t compute_pgm_hi;
176 	uint32_t compute_tba_lo;
177 	uint32_t compute_tba_hi;
178 	uint32_t compute_tma_lo;
179 	uint32_t compute_tma_hi;
180 	uint32_t compute_pgm_rsrc1;
181 	uint32_t compute_pgm_rsrc2;
182 	uint32_t compute_vmid;
183 	uint32_t compute_resource_limits;
184 	uint32_t compute_static_thread_mgmt_se0;
185 	uint32_t compute_static_thread_mgmt_se1;
186 	uint32_t compute_tmpring_size;
187 	uint32_t compute_static_thread_mgmt_se2;
188 	uint32_t compute_static_thread_mgmt_se3;
189 	uint32_t compute_restart_x;
190 	uint32_t compute_restart_y;
191 	uint32_t compute_restart_z;
192 	uint32_t compute_thread_trace_enable;
193 	uint32_t compute_misc_reserved;
194 	uint32_t compute_dispatch_id;
195 	uint32_t compute_threadgroup_id;
196 	uint32_t compute_relaunch;
197 	uint32_t compute_wave_restore_addr_lo;
198 	uint32_t compute_wave_restore_addr_hi;
199 	uint32_t compute_wave_restore_control;
200 	uint32_t reserved9;
201 	uint32_t reserved10;
202 	uint32_t reserved11;
203 	uint32_t reserved12;
204 	uint32_t reserved13;
205 	uint32_t reserved14;
206 	uint32_t reserved15;
207 	uint32_t reserved16;
208 	uint32_t reserved17;
209 	uint32_t reserved18;
210 	uint32_t reserved19;
211 	uint32_t reserved20;
212 	uint32_t reserved21;
213 	uint32_t reserved22;
214 	uint32_t reserved23;
215 	uint32_t reserved24;
216 	uint32_t reserved25;
217 	uint32_t reserved26;
218 	uint32_t reserved27;
219 	uint32_t reserved28;
220 	uint32_t reserved29;
221 	uint32_t reserved30;
222 	uint32_t reserved31;
223 	uint32_t reserved32;
224 	uint32_t reserved33;
225 	uint32_t reserved34;
226 	uint32_t compute_user_data_0;
227 	uint32_t compute_user_data_1;
228 	uint32_t compute_user_data_2;
229 	uint32_t compute_user_data_3;
230 	uint32_t compute_user_data_4;
231 	uint32_t compute_user_data_5;
232 	uint32_t compute_user_data_6;
233 	uint32_t compute_user_data_7;
234 	uint32_t compute_user_data_8;
235 	uint32_t compute_user_data_9;
236 	uint32_t compute_user_data_10;
237 	uint32_t compute_user_data_11;
238 	uint32_t compute_user_data_12;
239 	uint32_t compute_user_data_13;
240 	uint32_t compute_user_data_14;
241 	uint32_t compute_user_data_15;
242 	uint32_t cp_compute_csinvoc_count_lo;
243 	uint32_t cp_compute_csinvoc_count_hi;
244 	uint32_t reserved35;
245 	uint32_t reserved36;
246 	uint32_t reserved37;
247 	uint32_t cp_mqd_query_time_lo;
248 	uint32_t cp_mqd_query_time_hi;
249 	uint32_t cp_mqd_connect_start_time_lo;
250 	uint32_t cp_mqd_connect_start_time_hi;
251 	uint32_t cp_mqd_connect_end_time_lo;
252 	uint32_t cp_mqd_connect_end_time_hi;
253 	uint32_t cp_mqd_connect_end_wf_count;
254 	uint32_t cp_mqd_connect_end_pq_rptr;
255 	uint32_t cp_mqd_connect_endvi_sdma_mqd_pq_wptr;
256 	uint32_t cp_mqd_connect_end_ib_rptr;
257 	uint32_t reserved38;
258 	uint32_t reserved39;
259 	uint32_t cp_mqd_save_start_time_lo;
260 	uint32_t cp_mqd_save_start_time_hi;
261 	uint32_t cp_mqd_save_end_time_lo;
262 	uint32_t cp_mqd_save_end_time_hi;
263 	uint32_t cp_mqd_restore_start_time_lo;
264 	uint32_t cp_mqd_restore_start_time_hi;
265 	uint32_t cp_mqd_restore_end_time_lo;
266 	uint32_t cp_mqd_restore_end_time_hi;
267 	uint32_t disable_queue;
268 	uint32_t reserved41;
269 	uint32_t gds_cs_ctxsw_cnt0;
270 	uint32_t gds_cs_ctxsw_cnt1;
271 	uint32_t gds_cs_ctxsw_cnt2;
272 	uint32_t gds_cs_ctxsw_cnt3;
273 	uint32_t reserved42;
274 	uint32_t reserved43;
275 	uint32_t cp_pq_exe_status_lo;
276 	uint32_t cp_pq_exe_status_hi;
277 	uint32_t cp_packet_id_lo;
278 	uint32_t cp_packet_id_hi;
279 	uint32_t cp_packet_exe_status_lo;
280 	uint32_t cp_packet_exe_status_hi;
281 	uint32_t gds_save_base_addr_lo;
282 	uint32_t gds_save_base_addr_hi;
283 	uint32_t gds_save_mask_lo;
284 	uint32_t gds_save_mask_hi;
285 	uint32_t ctx_save_base_addr_lo;
286 	uint32_t ctx_save_base_addr_hi;
287 	uint32_t dynamic_cu_mask_addr_lo;
288 	uint32_t dynamic_cu_mask_addr_hi;
289 	uint32_t cp_mqd_base_addr_lo;
290 	uint32_t cp_mqd_base_addr_hi;
291 	uint32_t cp_hqd_active;
292 	uint32_t cp_hqd_vmid;
293 	uint32_t cp_hqd_persistent_state;
294 	uint32_t cp_hqd_pipe_priority;
295 	uint32_t cp_hqd_queue_priority;
296 	uint32_t cp_hqd_quantum;
297 	uint32_t cp_hqd_pq_base_lo;
298 	uint32_t cp_hqd_pq_base_hi;
299 	uint32_t cp_hqd_pq_rptr;
300 	uint32_t cp_hqd_pq_rptr_report_addr_lo;
301 	uint32_t cp_hqd_pq_rptr_report_addr_hi;
302 	uint32_t cp_hqd_pq_wptr_poll_addr_lo;
303 	uint32_t cp_hqd_pq_wptr_poll_addr_hi;
304 	uint32_t cp_hqd_pq_doorbell_control;
305 	uint32_t cp_hqd_pq_wptr;
306 	uint32_t cp_hqd_pq_control;
307 	uint32_t cp_hqd_ib_base_addr_lo;
308 	uint32_t cp_hqd_ib_base_addr_hi;
309 	uint32_t cp_hqd_ib_rptr;
310 	uint32_t cp_hqd_ib_control;
311 	uint32_t cp_hqd_iq_timer;
312 	uint32_t cp_hqd_iq_rptr;
313 	uint32_t cp_hqd_dequeue_request;
314 	uint32_t cp_hqd_dma_offload;
315 	uint32_t cp_hqd_sema_cmd;
316 	uint32_t cp_hqd_msg_type;
317 	uint32_t cp_hqd_atomic0_preop_lo;
318 	uint32_t cp_hqd_atomic0_preop_hi;
319 	uint32_t cp_hqd_atomic1_preop_lo;
320 	uint32_t cp_hqd_atomic1_preop_hi;
321 	uint32_t cp_hqd_hq_status0;
322 	uint32_t cp_hqd_hq_control0;
323 	uint32_t cp_mqd_control;
324 	uint32_t cp_hqd_hq_status1;
325 	uint32_t cp_hqd_hq_control1;
326 	uint32_t cp_hqd_eop_base_addr_lo;
327 	uint32_t cp_hqd_eop_base_addr_hi;
328 	uint32_t cp_hqd_eop_control;
329 	uint32_t cp_hqd_eop_rptr;
330 	uint32_t cp_hqd_eop_wptr;
331 	uint32_t cp_hqd_eop_done_events;
332 	uint32_t cp_hqd_ctx_save_base_addr_lo;
333 	uint32_t cp_hqd_ctx_save_base_addr_hi;
334 	uint32_t cp_hqd_ctx_save_control;
335 	uint32_t cp_hqd_cntl_stack_offset;
336 	uint32_t cp_hqd_cntl_stack_size;
337 	uint32_t cp_hqd_wg_state_offset;
338 	uint32_t cp_hqd_ctx_save_size;
339 	uint32_t cp_hqd_gds_resource_state;
340 	uint32_t cp_hqd_error;
341 	uint32_t cp_hqd_eop_wptr_mem;
342 	uint32_t cp_hqd_eop_dones;
343 	uint32_t reserved46;
344 	uint32_t reserved47;
345 	uint32_t reserved48;
346 	uint32_t reserved49;
347 	uint32_t reserved50;
348 	uint32_t reserved51;
349 	uint32_t reserved52;
350 	uint32_t reserved53;
351 	uint32_t reserved54;
352 	uint32_t reserved55;
353 	uint32_t iqtimer_pkt_header;
354 	uint32_t iqtimer_pkt_dw0;
355 	uint32_t iqtimer_pkt_dw1;
356 	uint32_t iqtimer_pkt_dw2;
357 	uint32_t iqtimer_pkt_dw3;
358 	uint32_t iqtimer_pkt_dw4;
359 	uint32_t iqtimer_pkt_dw5;
360 	uint32_t iqtimer_pkt_dw6;
361 	uint32_t iqtimer_pkt_dw7;
362 	uint32_t iqtimer_pkt_dw8;
363 	uint32_t iqtimer_pkt_dw9;
364 	uint32_t iqtimer_pkt_dw10;
365 	uint32_t iqtimer_pkt_dw11;
366 	uint32_t iqtimer_pkt_dw12;
367 	uint32_t iqtimer_pkt_dw13;
368 	uint32_t iqtimer_pkt_dw14;
369 	uint32_t iqtimer_pkt_dw15;
370 	uint32_t iqtimer_pkt_dw16;
371 	uint32_t iqtimer_pkt_dw17;
372 	uint32_t iqtimer_pkt_dw18;
373 	uint32_t iqtimer_pkt_dw19;
374 	uint32_t iqtimer_pkt_dw20;
375 	uint32_t iqtimer_pkt_dw21;
376 	uint32_t iqtimer_pkt_dw22;
377 	uint32_t iqtimer_pkt_dw23;
378 	uint32_t iqtimer_pkt_dw24;
379 	uint32_t iqtimer_pkt_dw25;
380 	uint32_t iqtimer_pkt_dw26;
381 	uint32_t iqtimer_pkt_dw27;
382 	uint32_t iqtimer_pkt_dw28;
383 	uint32_t iqtimer_pkt_dw29;
384 	uint32_t iqtimer_pkt_dw30;
385 	uint32_t iqtimer_pkt_dw31;
386 	uint32_t reserved56;
387 	uint32_t reserved57;
388 	uint32_t reserved58;
389 	uint32_t set_resources_header;
390 	uint32_t set_resources_dw1;
391 	uint32_t set_resources_dw2;
392 	uint32_t set_resources_dw3;
393 	uint32_t set_resources_dw4;
394 	uint32_t set_resources_dw5;
395 	uint32_t set_resources_dw6;
396 	uint32_t set_resources_dw7;
420 struct vi_mqd_allocation {  argument
421 	struct vi_mqd mqd;  argument