Lines Matching refs:mod2array
2228 uint32_t *modearray, *mod2array; in gfx_v8_0_tiling_mode_table_init() local
2234 mod2array = adev->gfx.config.macrotile_mode_array; in gfx_v8_0_tiling_mode_table_init()
2240 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2347 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2351 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2355 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2359 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2363 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2367 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2371 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2375 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2379 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2383 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2387 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2391 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2395 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2399 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2411 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2539 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2543 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2547 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2551 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2555 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2559 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2563 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2567 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2571 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2575 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2579 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2583 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2587 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2591 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2601 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2728 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2732 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2736 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2740 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2744 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2748 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2752 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2756 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2760 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2764 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2768 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2772 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2776 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2780 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2790 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2918 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2923 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2928 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2933 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2938 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2943 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2948 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2953 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2958 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2963 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2968 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2973 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2978 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2983 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
2993 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3120 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3125 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3130 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3135 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3140 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3145 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3150 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3155 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3160 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3165 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3170 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3175 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3180 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3185 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3195 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3302 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3306 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3310 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3314 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3318 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3322 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3326 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3330 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
3334 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
3338 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3342 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3346 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3350 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3354 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3366 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
3478 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3482 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3486 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3490 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3494 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3498 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3502 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3506 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
3510 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
3514 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3518 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3522 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3526 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3530 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v8_0_tiling_mode_table_init()
3542 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); in gfx_v8_0_tiling_mode_table_init()