321 				       struct amdgpu_firmware_info *ucode,  in amdgpu_ucode_init_single_fw()  argument
327 	if (NULL == ucode->fw)  in amdgpu_ucode_init_single_fw()
330 	ucode->mc_addr = mc_addr;  in amdgpu_ucode_init_single_fw()
331 	ucode->kaddr = kptr;  in amdgpu_ucode_init_single_fw()
333 	if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)  in amdgpu_ucode_init_single_fw()
336 	header = (const struct common_firmware_header *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
338 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_init_single_fw()
341 	    (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&  in amdgpu_ucode_init_single_fw()
342 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&  in amdgpu_ucode_init_single_fw()
343 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&  in amdgpu_ucode_init_single_fw()
344 	     ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&  in amdgpu_ucode_init_single_fw()
345 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&  in amdgpu_ucode_init_single_fw()
346 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&  in amdgpu_ucode_init_single_fw()
347 	     ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {  in amdgpu_ucode_init_single_fw()
348 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);  in amdgpu_ucode_init_single_fw()
350 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
352 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
353 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||  in amdgpu_ucode_init_single_fw()
354 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {  in amdgpu_ucode_init_single_fw()
355 		ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -  in amdgpu_ucode_init_single_fw()
358 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
360 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
361 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||  in amdgpu_ucode_init_single_fw()
362 		   ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {  in amdgpu_ucode_init_single_fw()
363 		ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;  in amdgpu_ucode_init_single_fw()
365 		memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +  in amdgpu_ucode_init_single_fw()
368 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
369 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {  in amdgpu_ucode_init_single_fw()
370 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;  in amdgpu_ucode_init_single_fw()
371 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,  in amdgpu_ucode_init_single_fw()
372 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
373 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {  in amdgpu_ucode_init_single_fw()
374 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;  in amdgpu_ucode_init_single_fw()
375 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,  in amdgpu_ucode_init_single_fw()
376 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
377 	} else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {  in amdgpu_ucode_init_single_fw()
378 		ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;  in amdgpu_ucode_init_single_fw()
379 		memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,  in amdgpu_ucode_init_single_fw()
380 		       ucode->ucode_size);  in amdgpu_ucode_init_single_fw()
386 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,  in amdgpu_ucode_patch_jt()  argument
394 	if (NULL == ucode->fw)  in amdgpu_ucode_patch_jt()
397 	comm_hdr = (const struct common_firmware_header *)ucode->fw->data;  in amdgpu_ucode_patch_jt()
398 	header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_patch_jt()
399 	dst_addr = ucode->kaddr +  in amdgpu_ucode_patch_jt()
402 	src_addr = (uint8_t *)ucode->fw->data +  in amdgpu_ucode_patch_jt()
414 	struct amdgpu_firmware_info *ucode = NULL;  in amdgpu_ucode_init_bo()  local
450 		ucode = &adev->firmware.ucode[i];  in amdgpu_ucode_init_bo()
451 		if (ucode->fw) {  in amdgpu_ucode_init_bo()
452 			header = (const struct common_firmware_header *)ucode->fw->data;  in amdgpu_ucode_init_bo()
453 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,  in amdgpu_ucode_init_bo()
458 				cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;  in amdgpu_ucode_init_bo()
459 				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,  in amdgpu_ucode_init_bo()
463 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);  in amdgpu_ucode_init_bo()
478 	struct amdgpu_firmware_info *ucode = NULL;  in amdgpu_ucode_fini_bo()  local
484 		ucode = &adev->firmware.ucode[i];  in amdgpu_ucode_fini_bo()
485 		if (ucode->fw) {  in amdgpu_ucode_fini_bo()
486 			ucode->mc_addr = 0;  in amdgpu_ucode_fini_bo()
487 			ucode->kaddr = NULL;  in amdgpu_ucode_fini_bo()