Lines Matching defs:amdgpu_crtc

388 struct amdgpu_crtc {  struct
389 	struct drm_crtc base;
390 	int crtc_id;
391 	bool enabled;
392 	bool can_tile;
393 	uint32_t crtc_offset;
394 	struct drm_gem_object *cursor_bo;
395 	uint64_t cursor_addr;
396 	int cursor_x;
397 	int cursor_y;
398 	int cursor_hot_x;
399 	int cursor_hot_y;
400 	int cursor_width;
401 	int cursor_height;
402 	int max_cursor_width;
403 	int max_cursor_height;
404 	enum amdgpu_rmx_type rmx_type;
405 	u8 h_border;
406 	u8 v_border;
407 	fixed20_12 vsc;
408 	fixed20_12 hsc;
409 	struct drm_display_mode native_mode;
410 	u32 pll_id;
412 	struct amdgpu_flip_work *pflip_works;
413 	enum amdgpu_flip_status pflip_status;
414 	int deferred_flip_completion;
416 	struct amdgpu_atom_ss ss;
417 	bool ss_enabled;
418 	u32 adjusted_clock;
419 	int bpc;
420 	u32 pll_reference_div;
421 	u32 pll_post_div;
422 	u32 pll_flags;
423 	struct drm_encoder *encoder;
424 	struct drm_connector *connector;
426 	u32 line_time;
427 	u32 wm_low;
428 	u32 wm_high;
429 	u32 lb_vblank_lead_lines;
430 	struct drm_display_mode hw_mode;
432 	struct hrtimer vblank_timer;
433 	enum amdgpu_interrupt_state vsync_timer_enabled;
435 	int otg_inst;
436 	struct drm_pending_vblank_event *event;