571 		struct drm_amdgpu_info_device dev_info;  in amdgpu_info_ioctl()  local
574 		memset(&dev_info, 0, sizeof(dev_info));  in amdgpu_info_ioctl()
575 		dev_info.device_id = dev->pdev->device;  in amdgpu_info_ioctl()
576 		dev_info.chip_rev = adev->rev_id;  in amdgpu_info_ioctl()
577 		dev_info.external_rev = adev->external_rev_id;  in amdgpu_info_ioctl()
578 		dev_info.pci_rev = dev->pdev->revision;  in amdgpu_info_ioctl()
579 		dev_info.family = adev->family;  in amdgpu_info_ioctl()
580 		dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;  in amdgpu_info_ioctl()
581 		dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;  in amdgpu_info_ioctl()
583 		dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;  in amdgpu_info_ioctl()
585 			dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;  in amdgpu_info_ioctl()
586 			dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;  in amdgpu_info_ioctl()
588 			dev_info.max_engine_clock = adev->clock.default_sclk * 10;  in amdgpu_info_ioctl()
589 			dev_info.max_memory_clock = adev->clock.default_mclk * 10;  in amdgpu_info_ioctl()
591 		dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;  in amdgpu_info_ioctl()
592 		dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *  in amdgpu_info_ioctl()
594 		dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;  in amdgpu_info_ioctl()
595 		dev_info._pad = 0;  in amdgpu_info_ioctl()
596 		dev_info.ids_flags = 0;  in amdgpu_info_ioctl()
598 			dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;  in amdgpu_info_ioctl()
600 			dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;  in amdgpu_info_ioctl()
609 		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;  in amdgpu_info_ioctl()
610 		dev_info.virtual_address_max =  in amdgpu_info_ioctl()
614 			dev_info.high_va_offset = AMDGPU_VA_HOLE_END;  in amdgpu_info_ioctl()
615 			dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;  in amdgpu_info_ioctl()
617 		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);  in amdgpu_info_ioctl()
618 		dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;  in amdgpu_info_ioctl()
619 		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;  in amdgpu_info_ioctl()
620 		dev_info.cu_active_number = adev->gfx.cu_info.number;  in amdgpu_info_ioctl()
621 		dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;  in amdgpu_info_ioctl()
622 		dev_info.ce_ram_size = adev->gfx.ce_ram_size;  in amdgpu_info_ioctl()
623 		memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],  in amdgpu_info_ioctl()
625 		memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],  in amdgpu_info_ioctl()
627 		dev_info.vram_type = adev->gmc.vram_type;  in amdgpu_info_ioctl()
628 		dev_info.vram_bit_width = adev->gmc.vram_width;  in amdgpu_info_ioctl()
629 		dev_info.vce_harvest_config = adev->vce.harvest_config;  in amdgpu_info_ioctl()
630 		dev_info.gc_double_offchip_lds_buf =  in amdgpu_info_ioctl()
634 			dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;  in amdgpu_info_ioctl()
635 			dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;  in amdgpu_info_ioctl()
636 			dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;  in amdgpu_info_ioctl()
637 			dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;  in amdgpu_info_ioctl()
638 			dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;  in amdgpu_info_ioctl()
639 			dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;  in amdgpu_info_ioctl()
640 			dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;  in amdgpu_info_ioctl()
641 			dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;  in amdgpu_info_ioctl()
643 		dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;  in amdgpu_info_ioctl()
644 		dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;  in amdgpu_info_ioctl()
645 		dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;  in amdgpu_info_ioctl()
646 		dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;  in amdgpu_info_ioctl()
647 		dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;  in amdgpu_info_ioctl()
648 		dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;  in amdgpu_info_ioctl()
649 		dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;  in amdgpu_info_ioctl()
651 		return copy_to_user(out, &dev_info,  in amdgpu_info_ioctl()
652 				    min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;  in amdgpu_info_ioctl()