Lines Matching defs:sym_hcb
1463 struct sym_hcb { struct
1464 struct lock lock;
1473 struct sym_ccbh ccb_head;
1474 struct sym_tcbh tcb_head;
1475 struct sym_lcbh lcb_head;
1481 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1482 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1488 u32 *badluntbl; /* Table physical address */
1489 u32 badlun_sa; /* SCRIPT handler BUS address */
1494 u32 hcb_ba;
1501 u32 scr_ram_seg;
1506 device_t device;
1513 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1514 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1515 sv_stest1;
1522 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1523 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1529 struct sym_tcb *target;
1531 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1538 u32 *targtbl;
1539 u32 targtbl_ba;
1544 struct cam_sim *sim;
1545 struct cam_path *path;
1550 struct resource *irq_res;
1551 struct resource *io_res;
1552 struct resource *mmio_res;
1553 struct resource *ram_res;
1554 int ram_id;
1555 void *intr;
1572 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1573 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1577 vm_offset_t mmio_ba; /* MMIO BUS address */
1578 int mmio_ws; /* MMIO Window size */
1580 vm_offset_t ram_ba; /* RAM BUS address */
1581 int ram_ws; /* RAM window size */
1589 u_char *scripta0; /* Copies of script and scripth */
1590 u_char *scriptb0; /* Copies of script and scripth */
1591 vm_offset_t scripta_ba; /* Actual script and scripth */
1592 vm_offset_t scriptb_ba; /* bus addresses. */
1593 vm_offset_t scriptb0_ba;
1594 u_short scripta_sz; /* Actual size of script A */
1595 u_short scriptb_sz; /* Actual size of script B */
1601 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1602 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1603 void (*fw_setup)(hcb_p np, const struct sym_fw *fw);
1604 void (*fw_patch)(hcb_p np);
1605 const char *fw_name;
1610 u_short device_id; /* PCI device id */
1611 u_char revision_id; /* PCI device revision id */
1612 u_int features; /* Chip features map */
1613 u_char myaddr; /* SCSI id of the adapter */
1614 u_char maxburst; /* log base 2 of dwords burst */
1615 u_char maxwide; /* Maximum transfer width */
1616 u_char minsync; /* Min sync period factor (ST) */
1617 u_char maxsync; /* Max sync period factor (ST) */
1618 u_char maxoffs; /* Max scsi offset (ST) */
1619 u_char minsync_dt; /* Min sync period factor (DT) */
1620 u_char maxsync_dt; /* Max sync period factor (DT) */
1621 u_char maxoffs_dt; /* Max scsi offset (DT) */
1622 u_char multiplier; /* Clock multiplier (1,2,4) */
1623 u_char clock_divn; /* Number of clock divisors */
1624 u32 clock_khz; /* SCSI clock frequency in KHz */
1625 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1632 u32 *squeue; /* Start queue virtual address */
1633 u32 squeue_ba; /* Start queue BUS address */
1634 u_short squeueput; /* Next free slot of the queue */
1635 u_short actccbs; /* Number of allocated CCBs */
1641 u_short dqueueget; /* Next position to scan */
1643 u32 *dqueue; /* Completion (done) queue */
1644 u32 dqueue_ba; /* Done queue BUS address */
1651 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1652 u_char msgin [8]; /* Buffer for MESSAGE IN */
1653 u32 lastmsg; /* Last SCSI message sent */
1654 u_char scratch; /* Scratch for SCSI receive */
1659 u_char usrflags; /* Miscellaneous user flags */
1660 u_char scsi_mode; /* Current SCSI BUS mode */
1661 u_char verbose; /* Verbosity for this controller*/
1662 u32 cache; /* Used for cache test at init. */
1667 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1668 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1669 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1677 SYM_QUEHEAD comp_ccbq;
1682 SYM_QUEHEAD cam_ccbq;
1713 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) argument