Lines Matching refs:Ri
99 #define Ri 7 /* register in instruction */ macro
705 /*50*/ { "push", FALSE, LONG, op1(Ri), 0 },
706 /*51*/ { "push", FALSE, LONG, op1(Ri), 0 },
707 /*52*/ { "push", FALSE, LONG, op1(Ri), 0 },
708 /*53*/ { "push", FALSE, LONG, op1(Ri), 0 },
709 /*54*/ { "push", FALSE, LONG, op1(Ri), 0 },
710 /*55*/ { "push", FALSE, LONG, op1(Ri), 0 },
711 /*56*/ { "push", FALSE, LONG, op1(Ri), 0 },
712 /*57*/ { "push", FALSE, LONG, op1(Ri), 0 },
714 /*58*/ { "pop", FALSE, LONG, op1(Ri), 0 },
715 /*59*/ { "pop", FALSE, LONG, op1(Ri), 0 },
716 /*5a*/ { "pop", FALSE, LONG, op1(Ri), 0 },
717 /*5b*/ { "pop", FALSE, LONG, op1(Ri), 0 },
718 /*5c*/ { "pop", FALSE, LONG, op1(Ri), 0 },
719 /*5d*/ { "pop", FALSE, LONG, op1(Ri), 0 },
720 /*5e*/ { "pop", FALSE, LONG, op1(Ri), 0 },
721 /*5f*/ { "pop", FALSE, LONG, op1(Ri), 0 },
779 /*91*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
780 /*92*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
781 /*93*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
782 /*94*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
783 /*95*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
784 /*96*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
785 /*97*/ { "xchg", FALSE, LONG, op2(A, Ri), 0 },
814 /*b0*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
815 /*b1*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
816 /*b2*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
817 /*b3*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
818 /*b4*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
819 /*b5*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
820 /*b6*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
821 /*b7*/ { "mov", FALSE, BYTE, op2(I, Ri), 0 },
823 /*b8*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
824 /*b9*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
825 /*ba*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
826 /*bb*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
827 /*bc*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
828 /*bd*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
829 /*be*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
830 /*bf*/ { "mov", FALSE, LONG, op2(Ilq, Ri), 0 },
1372 case Ri: in db_disasm()