Lines Matching +full:test2 +full:. +full:zeros
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
17 that is worth telling the compiler about). It may also contain comments.
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
29 from such an insn.
31 the assembler code.
33 for an insn.
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
48 predication.
50 md file.
51 * Iterators:: Using iterators to generate patterns from a template.
62 The front end reads the source code and builds a parse tree.
66 instruction patterns.
70 code.
75 named @code{define_insn} or a @code{define_expand}. The compiler will
78 template or operand constraints. Note that the names the compiler looks
81 named pattern it needs, it will abort.
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
93 replace, and rearrange the insns in the insn list. This is where the
95 example.
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
111 output, all wrapped up in a @code{define_insn} expression.
117 An optional name. The presence of a name indicate that this instruction
119 pass of the compiler. This pass knows certain names and will use
121 in the machine description.
124 where the name should go. Nameless instruction patterns are never
126 to be combined later on.
129 effect; they are equivalent to no name at all.
132 name beginning with the @samp{*} character. Such a name is used only
134 to having a nameless pattern for all other purposes.
138 RTL expressions which show what the instruction should look like. It is
141 operands of the instruction.
144 instruction pattern. If the vector has multiple elements, then the
146 elements described.
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
157 flags. The compiler needs to test these conditions during
159 available in a particular run.
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
167 certain hard registers or hard register combinations.
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
175 of C code to compute the output. @xref{Output Statement}.
179 this pattern. @xref{Insn Attributes}.
186 Here is an actual example of an instruction pattern, for the 68000/68020.
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
221 can be constructed using this pattern.
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
245 substitution of the operands.
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
255 pattern will not match at all.
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
261 expressions. In the case of a @code{define_expand}, any operand numbers
263 other operand numbers.
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
274 valid.
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
280 @code{VOIDmode}.
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
295 expression.
304 expression.
309 necessary. @xref{Side Effects}.
313 This expression is also a placeholder for operand number @var{n}.
315 insn.
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
322 identical-looking expression.
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
332 twice; once for the quotient pattern and once for the remainder pattern.
337 code.
341 operands are constructed from the patterns @var{operands}.
345 patterns @var{operands} match the operands of the expression.
375 because the expressions to be matched all contain two operands.
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
381 (operands[3])} to see which commutative operator was used.
386 deciding whether the expression to be matched ``has'' that mode.
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
397 is higher than that of the actual operands of the insn. This improves
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
403 never has any constraints because it is never reloaded as a whole.
406 their own.
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
416 expression.
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
425 this point. When matching an insn, it matches if the body of the insn
430 @code{parallel} that is the body of the insn. It is the responsibility
432 those listed in the @code{match_parallel}.
436 in a @code{parallel}. For example,
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
453 registers and memory locations.
473 @code{match_operator}.
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
489 different syntax.
492 operand @var{n} at that point in the string.
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
501 operand.
504 the constant is negated before printing.
507 memory reference, with the actual operand treated as the address. This may
510 as if it were a memory reference.
513 instruction.
516 entire compilation. This is useful for making local labels to be
518 assembler instructions.
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
534 each other, the output template must refer only to the lower-numbered operand.
537 operand.
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
548 it to do nothing.
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
558 instructions.
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
573 instruction pattern. For example, the opcodes may depend on the kinds of
575 machine instructions.
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
606 double-quoted string, it is automatically assumed to be C code. In that
608 doublequotes surrounding C string literals.
611 is @code{rtx []}.
614 based on whether an immediate operand is within a certain range. Be
616 integer on the host machine. If the host machine has more bits in an
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
627 that you declare locally and initialize yourself.
632 was matched. When this is so, the C code can test the variable
635 etc.).
638 for registers and @samp{clrmem} for memory locations. Here is how
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
681 that end in @samp{_operator}.
686 @code{match_operand} or @code{match_operator} specifies. In this
688 @var{mode}. Predicates can be called from C as ordinary two-argument
690 machine-specific code.
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
696 instructions as closely as possible. Reload cannot fix up operands
699 in the extra condition.
704 Most predicates handle their @var{mode} argument in a uniform manner.
706 any mode. If @var{mode} is anything else, then @var{op} must have the
708 @code{CONST_DOUBLE}. These RTL expressions always have
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
716 knowledge of how normal predicates treat modes. It can also diagnose
719 without specifying a mode.
722 are called @dfn{special}. The generic predicates
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
730 functions.
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
743 This predicate allows any sort of constant that fits in @var{mode}.
745 must be constant.
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
758 constants.
763 register.
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
773 a limitation in the machine-description reader.
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
790 options. @xref{Misc}.
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
815 @code{address_operand}. Note that @var{exp} does not necessarily have
816 the mode @var{mode}.
822 expression. New uses of this predicate are discouraged, because
824 an @code{indirect_operand} does or does not allow. If a target has
827 hardware's requirements explicitly.
832 onto the stack. This will be a @code{MEM} which refers to
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
840 off the stack. Again, this will be a @code{MEM} referring to
842 expression. However, this time @code{STACK_POP_CODE} is expected.
847 operands.
850 This predicate allows any immediate or register operand valid for @var{mode}.
854 This predicate allows any register or memory operand valid for @var{mode}.
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
868 expression code.
876 @code{ge}, @code{geu}.
886 expressed precisely using the generic predicates. You can define
888 @code{define_special_predicate} expressions. These expressions have
894 @code{match_operand} or @code{match_operator} expressions.
898 operand @var{op}, false if it does not. This expression can only use
905 @var{op}. The operand number and constraint are ignored. Due to
907 predicates and predicates that have already been defined.
911 subexpression of @var{op} has one of a given list of RTX codes.
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
923 characters it is the result of the previous character. A digit
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
928 extracted by the complete string. It is not possible to extract
930 object.
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
960 execute @samp{@w{return true}} for the predicate to allow the operand.
962 code block that was checked in the RTL expression.
967 codes are possibly allowed. You should always make this explicit in
969 @code{MATCH_CODE}.
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1007 kind of constant fits in the requested mode. This is because
1009 stringent value checks anyway. If you need the exact same treatment
1013 @code{immediate_operand}.
1017 by @command{genrecog}.
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1035 constraints for the operands allowed. The constraints allow you to
1037 predicate.
1048 @code{asm} operands.
1054 have. Constraints can also require two operands to match.
1058 the addressing register.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Class Preferences:: Constraints guide which hard register to put things in.
1065 * Modifiers:: More precise control over effects of constraints.
1066 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1067 * Machine Constraints:: Existing constraints for some particular machines.
1068 * Define Constraints:: How to define machine-specific constraints.
1069 * C Constraint Interface:: How to test constraints from C code.
1075 * Simple Constraints:: Basic use of constraints.
1076 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1077 * Modifiers:: More precise control over effects of constraints.
1078 * Machine Constraints:: Special constraints for some particular machines.
1087 which describes one kind of operand that is permitted. Here are
1093 except the first. This enables each alternative for different operands to
1095 number of constraints and modifiers.
1101 supports in general.
1103 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1109 @dfn{offsettable}. This means that adding a small integer (actually,
1112 address.
1119 address is not offsettable. More complicated indirect/indexed
1121 addressing modes that the machine supports.
1126 and @samp{>} (if the target machine has preincrement addressing).
1130 A memory operand that is not offsettable. In other words, anything that
1131 would fit the @samp{m} constraint but not the @samp{o} constraint.
1136 postdecrement) is allowed. In inline @code{asm} this constraint is only
1138 handle the side-effects. Not using an operand with @samp{<} in constraint
1141 or would be performed more than once. Furthermore, on some targets
1144 or @code{%P0} on IA-64.
1149 postincrement) is allowed. In inline @code{asm} the same restrictions
1150 as for @samp{<} apply.
1156 register.
1161 An immediate integer operand (one with constant value) is allowed.
1163 assembly time or later.
1167 An immediate integer operand with a known numeric value is allowed.
1169 than a word wide. Constraints for these operands should use @samp{n}
1170 rather than @samp{i}.
1176 explicit integer values in specified ranges. For example, on the
1177 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1179 instructions.
1185 that of the host machine (on which the compiler is running).
1190 @code{const_vector}) is allowed.
1196 permit immediate floating operands in particular ranges of values.
1201 allowed.
1205 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1206 better code to be generated.
1211 using the register. This is because the load into the register can be
1212 done with a @samp{moveq} instruction. We arrange for this to happen
1215 constraints.
1220 registers that are not general registers.
1226 @code{general_operand}. This is normally used in the constraint of
1228 require a scratch register.
1231 Any operand whatsoever is allowed.
1237 An operand that matches the specified operand number is allowed. If a
1239 digit should come last.
1241 This number is allowed to be more than a single digit. If multiple
1243 decimal integer. There is scant chance for ambiguity, since to-date
1245 either operand 1 @emph{or} operand 0. Should this be desired, one
1246 can use multiple alternatives instead.
1253 considered separate in the RTL insn. For example, an add insn has two
1257 which @code{asm} distinguishes. For example, an add instruction uses
1267 Matching constraints are used in these circumstances.
1269 operand and one output-only operand. Moreover, the digit must be a
1271 constraint.
1275 are identical-looking RTL expressions. But in a few special cases
1276 specific kinds of dissimilarity are allowed. For example, @code{*x}
1277 as an input operand will match @code{*x++} as an output operand.
1279 use the output-operand's number when printing the operand.
1287 An operand that is a valid memory address is allowed. This is
1288 for ``load address'' and ``push address'' instructions.
1292 as the predicate in the @code{match_operand}. This predicate interprets
1294 reference for which the address would be valid.
1300 particular classes of registers or other arbitrary operand types.
1302 for data, address and floating point registers.
1307 its constraint. But a failure to do so does not prevent the pattern
1308 from applying to an insn. Instead, it directs the compiler to modify
1309 the code so that the constraint will be satisfied. Usually this is
1310 done by copying an operand into a register.
1337 identical. If we are considering an insn of the form
1348 contain two identical subexpressions in the right place. The pattern would
1349 say, ``That does not look like an add instruction; try other patterns''.
1351 is something wrong with it''. It would direct the reload pass of the
1352 compiler to generate additional insns to make the constraint true. The
1368 that operand. (When multiple alternatives are in use, each pattern must,
1370 alternative which can handle that combination of operands.) The
1373 reloading any possible operand so that it will fit.
1378 there is no problem: reloading is never necessary for this operand.
1381 registers is safe provided its predicate rejects registers.
1384 provided its constraints include the letter @samp{i}. If any possible
1387 more selective.
1390 Any operand expression can be reloaded by copying it into a register.
1392 certain to be safe. It need not permit all classes of registers; the
1394 proper class in order to make an instruction valid.
1400 address into a register. So if the constraint uses the letter
1401 @samp{o}, all memory references are taken care of.
1405 hold it as preinitialized data. Then the memory reference can be used
1406 in place of the constant. So if the constraint uses the letters
1407 @samp{o} or @samp{m}, constant operands are not a problem.
1412 the register will be replaced with the constant. If the predicate does
1414 compiler will crash. Thus the predicate must always recognize any
1415 objects allowed by the constraint.
1419 not permit them, it can make the compiler crash. When this operand happens
1421 how to copy a register temporarily into memory.
1424 operand. For example, the MIPS processor at ISA level 3 supports an
1427 extended. This predicate for the input operands accepts a
1428 @code{sign_extend} of an @code{SImode} register. Write the constraint
1430 @code{sign_extend}.
1438 operands. For example, on the 68000, a logical-or instruction can combine
1441 another.
1443 These constraints are represented as multiple alternatives. An alternative
1444 can be described by a series of letters for each operand. The overall
1447 the second alternative, a comma, and so on until the last alternative.
1461 2. The second alternative has @samp{d} (data register) for operand 0,
1462 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1464 meaning is explained in the next section (@pxref{Class Preferences}).
1468 If all the operands fit any one alternative, the instruction is valid.
1470 must be added to copy the operands so that that alternative applies.
1471 The alternative requiring the least copying is chosen. If two alternatives
1472 need the same amount of copying, the one that comes first is chosen.
1480 as a choice when no alternative applies exactly. The compiler regards
1482 in it.
1487 Disparage severely the alternative that the @samp{!} appears in.
1489 but if reloading is needed, some other alternative will be used.
1495 alternative was matched. When this is so, the C code for writing the
1498 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1510 allocated to. The compiler examines the constraints that apply to the
1512 letters such as @samp{d} and @samp{a} that specify classes of registers.
1513 The pseudo register is put in whichever class gets the most ``votes''.
1515 favor of a general register. The machine description says which registers
1516 are considered general.
1519 classes are defined. Then none of this complexity is relevant.
1528 Here are constraint modifier characters.
1534 value is discarded and replaced by output data.
1538 Means that this operand is both read and written by the instruction.
1542 which are outputs from it. @samp{=} identifies an output; @samp{+}
1544 are assumed to be input only.
1547 first character of the constraint string.
1554 finished using the input operands. Therefore, this operand may not lie
1556 address.
1558 @samp{&} applies only to the alternative in which it is written. In
1560 requires @samp{&} while others do not. See, for example, the
1561 @samp{movdf} insn of the 68000.
1564 use as an input occurs before the early result is written. Adding
1566 when only some of the inputs can be affected by the earlyclobber.
1567 See, for example, the @samp{mulsi3} insn of the ARM@.
1569 @samp{&} does not obviate the need to write @samp{=}.
1574 following operand. This means that the compiler may interchange the
1576 constraints.
1580 arguments. Here for example, is how the 68000 halfword-add
1592 the compiler may fail. Note that you need not use the modifier if
1594 time in the reload pass. The modifier is not operational after
1597 @samp{%} to make the intended insn match.
1602 ignored as a constraint. They are significant only for choosing
1603 register preferences.
1608 register preferences. @samp{*} has no effect on the meaning of the
1609 constraint as a constraint, and no effect on reloading.
1614 copying it into an address register. While either kind of register is
1617 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1619 register preferences.
1638 people reading your code. Failing that, use the constraint letters
1639 that usually have very similar meanings across architectures. The most
1643 immediate-constant format.
1645 Each architecture defines additional constraints. These constraints
1648 particularly useful for @code{asm}. Here is a summary of some of the
1651 constraints that aren't. The compiler source file mentioned in the
1653 the meanings of that architecture's constraints.
1656 @item ARM family---@file{config/arm/arm.h}
1674 instruction. That is, an integer in the range 0 to 255 rotated by a
1703 A memory reference suitable for iWMMXt load/store instructions.
1706 A memory reference suitable for the ARMv4 ldrsb instruction.
1709 @item AVR family---@file{config/avr/constraints.md}
1721 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1772 A memory address based on Y or Z pointer with displacement.
1775 @item Epiphany---@file{config/epiphany/constraints.md}
1778 An unsigned 16-bit constant.
1781 An unsigned 5-bit constant.
1784 A signed 11-bit constant.
1787 A signed 11-bit constant added to @minus{}1.
1788 Can only match when the @option{-m1reg-@var{reg}} option is active.
1791 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1792 being a block of trailing zeroes.
1793 Can only match when the @option{-m1reg-@var{reg}} option is active.
1796 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1797 rest being zeroes. Or to put it another way, one less than a power of two.
1798 Can only match when the @option{-m1reg-@var{reg}} option is active.
1801 Constant for arithmetic/logical operations.
1803 no symbols / expressions needing relocations are allowed.
1806 Symbolic constant for call/jump instruction.
1809 The register class usable in short insns. This is a register class
1810 constraint, and can thus drive register allocation.
1812 in effect.
1816 sibcall call address. I.e., a caller-saved register.
1819 Core control register class.
1822 The register group usable in short insns.
1824 passively matches suitable registers, and doesn't drive register allocation.
1828 Constant suitable for the addsi3_r pattern. This is a valid offset
1829 For byte, halfword, or word addressing.
1833 Matches the return address if it can be replaced with the link register.
1836 Matches the integer condition code register.
1839 Matches the return address if it is in a stack slot.
1843 @code{UNSPEC_FP_MODE}.
1846 @item CR16 Architecture---@file{config/cr16/cr16.h}
1880 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1951 @item picoChip family---@file{picochip.h}
1954 Stack register.
1957 Pointer register. A register which can be used to access memory without
1958 supplying an offset. Any other register can be used to access memory,
1959 but will need a constant offset. In the case of the offset being zero,
1961 size.
1964 A twin register. A register which may be paired with an adjacent
1965 register to create a 32-bit register.
1968 Any absolute memory address (e.g., symbolic constant, symbolic
1969 constant + offset).
1972 4-bit signed integer.
1975 4-bit unsigned integer.
1978 8-bit signed integer.
1981 Any constant whose absolute value is no greater than 4-bits.
1987 16-bit signed integer.
1991 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
2072 Memory operand.
2073 Normally, @code{m} does not allow addresses that update the base register.
2077 accesses the operand exactly once. The @code{asm} statement must also
2079 corresponding load or store instruction. For example:
2091 is not.
2095 automodification of the base register. This used to be useful when
2098 as @samp{m} without @samp{<} and @samp{>}.
2131 Vector constant that is all zeros.
2135 @item Intel 386---@file{config/i386/constraints.md}
2140 @code{si}, @code{di}, @code{bp}, @code{sp}).
2143 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2144 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2148 @code{c}, and @code{d}.
2153 access: that is, any general register except the stack pointer.
2157 The @code{a} register.
2160 The @code{b} register.
2163 The @code{c} register.
2166 The @code{d} register.
2169 The @code{si} register.
2172 The @code{di} register.
2175 The @code{a} and @code{d} registers. This class is used for instructions
2176 that return double word results in the @code{ax:dx} register pair. Single
2177 word values will be allocated either in @code{ax} or @code{dx}.
2190 or @code{dx}. You have to use the following variant instead:
2203 Any 80387 floating-point (stack) register.
2206 Top of 80387 floating-point stack (@code{%st(0)}).
2209 Second from top of 80387 floating-point stack (@code{%st(1)}).
2212 Any MMX register.
2215 Any SSE register.
2218 First SSE register (@code{%xmm0}).
2222 Any SSE register, when SSE2 is enabled.
2225 Any SSE register, when SSE2 and inter-unit moves are enabled.
2228 Any MMX register, when inter-unit moves are enabled.
2232 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2235 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2238 Signed 8-bit integer constant.
2241 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2244 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2248 instructions).
2252 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2256 Standard 80387 floating point constant.
2259 Standard SSE floating point constant.
2264 instructions).
2269 instructions).
2273 @item Intel IA-64---@file{config/ia64/ia64.h}
2294 Memory operand. If used together with @samp{<} or @samp{>},
2296 require printing with @samp{%Pn} on IA-64.
2332 Memory operand except postincrement and postdecrement. This is
2334 or @samp{>}.
2337 @item FRV---@file{config/frv/frv.h}
2340 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2343 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2347 @code{icc0} to @code{icc3}).
2350 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2353 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2355 mode larger than 4 bytes.
2358 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2361 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2363 mode larger than 4 bytes.
2366 Register in the class @code{LR_REG} (the @code{lr} register).
2369 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2371 the use of a machine mode larger than 8 bytes.
2374 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2377 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2380 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2383 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2386 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2388 the use of a machine mode larger than 8 bytes.
2391 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2394 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2397 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2400 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2418 12-bit signed integer constant that is negative---i.e.@: in the
2425 12-bit signed integer constant that is greater than zero---i.e.@: in the
2426 range of 1 to 2047.
2430 @item Blackfin family---@file{config/bfin/constraints.md}
2439 A call clobbered P register.
2442 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2443 register. If it is @code{A}, then the register P0.
2452 Accumulator register.
2455 Even-numbered accumulator register.
2458 Odd-numbered accumulator register.
2470 Registers used for circular buffering, i.e. I, B, or L registers.
2473 The CC register.
2476 LT0 or LT1.
2479 LC0 or LC1.
2482 LB0 or LB1.
2485 Any D, P, B, M, I or L register.
2489 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2492 Any register except accumulators or CC.
2519 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2523 use with either accumulator.
2527 use only with accumulator A1.
2530 Constant 255.
2533 Constant 65535.
2536 An integer constant with exactly a single bit set.
2539 An integer constant with all bits set except exactly one.
2544 Any SYMBOL_REF.
2547 @item M32C---@file{config/m32c/m32c.c}
2552 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2559 Any control register, when they're 24 bits wide.
2565 $r0, $r1, $r2, $r3.
2568 $r0 or $r2, or $r2r0 for 32 bit values.
2571 $r1 or $r3, or $r3r1 for 32 bit values.
2574 A register that can hold a 64 bit value.
2586 Address registers when they're 16 bits wide.
2589 Address registers when they're 24 bits wide.
2592 Registers that can hold QI values.
2595 Registers that can be used with displacements ($a0, $a1, $sb).
2598 Registers that can hold 32 bit values.
2601 Registers that can hold 16 bit values.
2605 registers.
2608 $r0 through R1, plus $a0 and $a1.
2611 The flags register.
2614 The memory-based pseudo-registers $mem0 through $mem15.
2618 bit registers for m32cm, m32c).
2621 Matches multiple registers in a PARALLEL to form a larger register.
2622 Used to match function return values.
2649 An 8 bit value with exactly one bit set.
2652 A 16 bit value with exactly one bit set.
2655 The common src/dest memory addressing modes.
2658 Memory addressed using $a0 or $a1.
2661 Memory addressed with immediate addresses.
2664 Memory addressed using the stack pointer ($sp).
2667 Memory addressed using the frame base register ($fb).
2670 Memory addressed using the small base register ($sb).
2676 @item MeP---@file{config/mep/constraints.md}
2680 The $sp register.
2683 The $tp register.
2686 Any control register.
2689 Either the $hi or the $lo register.
2692 Coprocessor registers that can be directly loaded ($c0-$c15).
2695 Coprocessor registers that can be moved to each other.
2698 Coprocessor registers that can be moved to core registers.
2701 The $hi register.
2704 The $rpc register.
2707 The $lo register.
2710 Registers which can be used in $tp-relative addressing.
2713 The $gp register.
2716 The coprocessor registers.
2719 The coprocessor control registers.
2722 The $0 register.
2725 User-defined register set A.
2728 User-defined register set B.
2731 User-defined register set C.
2734 User-defined register set D.
2737 Offsets for $gp-rel addressing.
2740 Constants that can be used directly with boolean insns.
2743 Constants that can be moved directly to registers.
2746 Small constants that can be added to registers.
2749 Long shift counts.
2752 Small constants that can be compared to registers.
2755 Constants that can be loaded into the top half of registers.
2758 Signed 8-bit immediates.
2761 Symbols encoded for $tp-rel or $gp-rel addressing.
2764 Non-constant addresses for loading/saving coprocessor registers.
2767 The top half of a symbol's value.
2770 A register indirect address without offset.
2773 Symbolic references to the control bus.
2777 @item MicroBlaze---@file{config/microblaze/constraints.md}
2780 A general register (@code{r0} to @code{r31}).
2783 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2787 @item MIPS---@file{config/mips/constraints.md}
2790 An address register. This is equivalent to @code{r} unless
2791 generating MIPS16 code.
2794 A floating-point register (if available).
2797 Formerly the @code{hi} register. This constraint is no longer supported.
2800 The @code{lo} register. Use this register to store values that are
2801 no bigger than a word.
2804 The concatenated @code{hi} and @code{lo} registers. Use this register
2805 to store doubleword values.
2808 A register suitable for use in an indirect jump. This will always be
2809 @code{$25} for @option{-mabicalls}.
2812 Register @code{$3}. Do not use this constraint in new code;
2813 it is retained only for compatibility with glibc.
2816 Equivalent to @code{r}; retained for backwards compatibility.
2819 A floating-point condition code register.
2822 A signed 16-bit constant (for arithmetic instructions).
2825 Integer zero.
2828 An unsigned 16-bit constant (for logic instructions).
2831 A signed 32-bit constant in which the lower 16 bits are zero.
2832 Such constants can be loaded using @code{lui}.
2836 or @code{ori}.
2839 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2842 A signed 15-bit constant.
2845 A constant in the range 1 to 65535 (inclusive).
2848 Floating-point zero.
2851 An address that can be used in a non-macro load or store.
2854 @item Motorola 680x0---@file{config/m68k/constraints.md}
2942 @item Moxie---@file{config/moxie/constraints.md}
2954 A constant in the range of 0 to 255.
2957 A constant in the range of 0 to @minus{}255.
2961 @item PDP-11---@file{config/pdp11/constraints.md}
2964 Floating point registers AC0 through AC3. These can be loaded from/to
2965 memory with a single instruction.
2968 Odd numbered general registers (R1, R3, R5). These are used for
2969 16-bit multiply operations.
2972 Any of the floating point registers (AC0 through AC5).
2975 Floating point constant 0.
2978 An integer constant that fits in 16 bits.
2981 An integer constant whose low order 16 bits are zero.
2985 @samp{I} or @samp{J}.
2988 The integer constant 1.
2991 The integer constant @minus{}1.
2994 The integer constant 0.
2999 variable-length shift.
3003 offset) after the opcode.
3006 A memory reference that is encoded within the opcode.
3010 @item RL78---@file{config/rl78/constraints.md}
3014 An integer constant in the range 1 @dots{} 7.
3016 An integer constant in the range 0 @dots{} 255.
3020 The integer constant 1.
3022 The integer constant -1.
3024 The integer constant 0.
3026 The integer constant 2.
3028 The integer constant -2.
3030 An integer constant in the range 1 @dots{} 15.
3032 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3034 The synthetic compare types--gt, lt, ge, and le.
3036 A memory reference with an absolute address.
3038 A memory reference using @code{BC} as a base register, with an optional offset.
3040 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3042 A memory reference using any 16-bit register pair for the address, for calls.
3044 A memory reference using @code{DE} as a base register, with an optional offset.
3046 A memory reference using @code{DE} as a base register, without any offset.
3048 Any memory reference to an address in the far address space.
3050 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3052 …mory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3054 A memory reference using @code{HL} as a base register, without any offset.
3056 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3058 Any memory reference to an address in the near address space.
3060 The @code{AX} register.
3062 The @code{BC} register.
3064 The @code{DE} register.
3066 @code{A} through @code{L} registers.
3068 The @code{SP} register.
3070 The @code{HL} register.
3072 The 16-bit @code{R8} register.
3074 The 16-bit @code{R10} register.
3076 The registers reserved for interrupts (@code{R24} to @code{R31}).
3078 The @code{A} register.
3080 The @code{B} register.
3082 The @code{C} register.
3084 The @code{D} register.
3086 The @code{E} register.
3088 The @code{H} register.
3090 The @code{L} register.
3092 The virtual registers.
3094 The @code{PSW} register.
3096 The @code{X} register.
3100 @item RX---@file{config/rx/constraints.md}
3104 pre/post increment/decrement addressing.
3107 A symbol reference.
3110 A constant in the range @minus{}256 to 255, inclusive.
3113 A constant in the range @minus{}128 to 127, inclusive.
3116 A constant in the range @minus{}32768 to 32767, inclusive.
3119 A constant in the range @minus{}8388608 to 8388607, inclusive.
3122 A constant in the range 0 to 15, inclusive.
3127 @item SPARC---@file{config/sparc/sparc.h}
3131 lower floating-point register on the SPARC-V9 architecture.
3134 Floating-point register. It is equivalent to @samp{f} on the
3136 floating-point registers on the SPARC-V9 architecture.
3139 Floating-point condition code register.
3142 Lower floating-point register. It is only valid on the SPARC-V9
3143 architecture when the Visual Instruction Set is available.
3146 Floating-point register. It is only valid on the SPARC-V9 architecture
3147 when the Visual Instruction Set is available.
3150 64-bit global or out register for the SPARC-V8+ architecture.
3173 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3214 @item SPU---@file{config/spu/spu.h}
3217 …which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3220 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3223 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3226 An immediate which can be loaded with @code{fsmbi}.
3229 …which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3232 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3235 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3238 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3241 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3244 An unsigned 7-bit constant for conversion/nop/channel instructions.
3247 A signed 10-bit constant for most arithmetic instructions.
3250 A signed 16 bit immediate for @code{stop}.
3253 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3256 An unsigned 7-bit constant whose 3 least significant bits are 0.
3265 Call operand, symbol, for relative calls.
3268 Call operand, const_int, for absolute calls.
3271 … which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3274 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3277 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3280 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3284 @item S/390 and zSeries---@file{config/s390/s390.h}
3308 Value appropriate as displacement.
3310 @item (0..4095)
3312 @item (@minus{}524288..524287)
3317 Constant integer with a value of 0x7fffffff.
3320 Multiple letter constraint followed by 4 parameter letters.
3322 @item 0..9:
3332 has a value different from its other parts.
3335 Memory reference without index register and with short displacement.
3338 Memory reference with index register and short displacement.
3341 Memory reference without index register but with long displacement.
3344 Memory reference with index register and long displacement.
3347 Pointer with short displacement.
3350 Pointer with long displacement.
3353 Shift count operand.
3357 @item Score family---@file{config/score/score.h}
3360 Registers from r0 to r32.
3363 Registers from r0 to r16.
3366 r8---r11 or r22---r27 registers.
3369 hi register.
3372 lo register.
3375 hi + lo register.
3378 cnt register.
3381 lcb register.
3384 scb register.
3387 cnt + lcb + scb register.
3390 cr0---cr15 register.
3393 cp1 registers.
3396 cp2 registers.
3399 cp3 registers.
3402 cp1 + cp2 + cp3 registers.
3405 High 16-bit constant (32-bit constant with 16 LSBs zero).
3408 Unsigned 5 bit integer (in the range 0 to 31).
3411 Unsigned 16 bit integer (in the range 0 to 65535).
3414 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3417 Unsigned 14 bit integer (in the range 0 to 16383).
3420 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3423 Any SYMBOL_REF.
3426 @item Xstormy16---@file{config/stormy16/stormy16.h}
3429 Register r0.
3432 Register r1.
3435 Register r2.
3438 Register r8.
3441 Registers r0 through r7.
3444 Registers r0 and r1.
3447 The carry register.
3450 Registers r8 and r9.
3453 A constant between 0 and 3 inclusive.
3456 A constant that has exactly one bit set.
3459 A constant that has exactly one bit clear.
3462 A constant between 0 and 255 inclusive.
3465 A constant between @minus{}255 and 0 inclusive.
3468 A constant between @minus{}3 and 0 inclusive.
3471 A constant between 1 and 4 inclusive.
3474 A constant between @minus{}4 and @minus{}1 inclusive.
3477 A memory reference that is a stack push.
3480 A memory reference that is a stack pop.
3483 A memory reference that refers to a constant address of known value.
3486 The register indicated by Rx (not implemented yet).
3489 A constant that is not between 2 and 15 inclusive.
3492 The constant 0.
3496 @item TI C6X family---@file{config/c6x/constraints.md}
3499 Register file A (A0--A31).
3502 Register file B (B0--B31).
3506 higher, A1 and A2 otherwise).
3509 Predicate registers in register file B (B0--B2).
3512 A call-used register in register file B (B0--B9, B16--B31).
3516 plus A0 if not C64X or higher).
3519 Register file B, excluding predicate registers (B3--B31).
3522 Integer constant in the range 0 @dots{} 15.
3525 Integer constant in the range 0 @dots{} 31.
3528 Integer constant in the range @minus{}31 @dots{} 0.
3531 Integer constant in the range @minus{}16 @dots{} 15.
3534 Integer constant that can be the operand of an ADDA or a SUBA insn.
3537 Integer constant in the range 0 @dots{} 65535.
3540 Integer constant in the range @minus{}32768 @dots{} 32767.
3543 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3546 Integer constant that is a valid mask for the clr instruction.
3549 Integer constant that is a valid mask for the set instruction.
3552 Memory location with A base register.
3555 Memory location with B base register.
3559 On C64x+ targets, a GP-relative small data reference.
3562 Any kind of @code{SYMBOL_REF}, for use in a call address.
3565 Any kind of immediate operand, unless it matches the S0 constraint.
3568 Memory location with B base register, but not using a long offset.
3571 A memory operand with an address that can't be used in an unaligned access.
3575 Register B14 (aka DP).
3579 @item TILE-Gx---@file{config/tilegx/constraints.md}
3593 register, from r0 to r10.
3596 Signed 8-bit integer constant.
3599 Signed 16-bit integer constant.
3602 Unsigned 16-bit integer constant.
3606 (@minus{}129 @dots{} 126).
3609 Memory operand. If used together with @samp{<} or @samp{>}, the
3611 and @samp{%in} on TILE-Gx. For example:
3618 A bit mask suitable for the BFINS instruction.
3621 Integer constant that is a byte tiled out eight times.
3624 The integer zero constant.
3627 Integer constant that is a sign-extended byte tiled out as four shorts.
3631 (@minus{}129 @dots{} 126), but excluding -1.
3634 Integer constant that has all 1 bits consecutive and starting at bit 0.
3637 A 16-bit fragment of a got, tls, or pc-relative reference.
3640 Memory operand except postincrement. This is roughly the same as
3641 @samp{m} when not used together with @samp{<} or @samp{>}.
3644 An 8-element vector constant with identical elements.
3647 A 4-element vector constant with identical elements.
3650 The integer constant 0xffffffff.
3653 The integer constant 0xffffffff00000000.
3657 @item TILEPro---@file{config/tilepro/constraints.md}
3671 register, from r0 to r10.
3674 Signed 8-bit integer constant.
3677 Signed 16-bit integer constant.
3680 Nonzero integer constant with low 16 bits zero.
3684 (@minus{}129 @dots{} 126).
3687 Memory operand. If used together with @samp{<} or @samp{>}, the
3689 and @samp{%in} on TILEPro. For example:
3696 A bit mask suitable for the MM instruction.
3699 Integer constant that is a byte tiled out four times.
3702 The integer zero constant.
3705 Integer constant that is a sign-extended byte tiled out as two shorts.
3709 (@minus{}129 @dots{} 126), but excluding -1.
3713 reference.
3716 Memory operand except postincrement. This is roughly the same as
3717 @samp{m} when not used together with @samp{<} or @samp{>}.
3720 A 4-element vector constant with identical elements.
3723 A 2-element vector constant with identical elements.
3727 @item Xtensa---@file{config/xtensa/constraints.md}
3760 alternatives for machine-specific reasons. This is useful when adding
3763 option.
3765 If an insn alternative is disabled, then it will never be used. The
3767 unsatisfiable.
3774 A definition of the @code{enabled} insn attribute. The attribute is
3775 defined as usual using the @code{define_attr} command. This
3776 definition should be based on other insn attributes and/or target flags.
3779 @code{(const_int 0)} otherwise.
3783 not. E.g. @code{cpu_facility} as in the example below.
3787 circumstances. (Note: It obviously only makes sense for definitions
3788 with more than one alternative. Otherwise the insn pattern should be
3789 disabled or enabled using the insn condition.)
3792 E.g. the following two patterns could easily be merged using the @code{enabled}
3854 non-register constraints. Within the latter category, constraints
3856 be specially marked, to give @code{reload} more information.
3860 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3861 must begin with a letter or underscore.
3865 name. For example, if @code{x} is defined as a constraint name,
3866 @code{xy} may not be, and vice versa. As a consequence of this rule,
3868 @samp{E F V X g i m n o p r s}.
3870 Register constraints correspond directly to register classes.
3871 @xref{Register Classes}. There is thus not much flexibility in their
3872 definitions.
3875 All three arguments are string constants.
3877 @code{match_operand} expressions. If @var{name} is a multi-letter
3879 with the same letter. @var{regclass} can be either the
3881 or a C expression which evaluates to the appropriate register class.
3883 look at the operand. The usual use of expressions is to map some
3885 is not available on a given subarchitecture.
3888 constraint. Docstrings are explained further below.
3893 constraint matches.
3898 immediately after the name for these expressions. @var{exp} is an RTL
3900 definitions. @xref{Defining Predicates}, for details. If it
3902 doesn't. Constraint expressions should indicate which RTL codes they
3903 might match, just like predicate expressions.
3910 The RTL object defining the operand.
3912 The machine mode of @var{op}.
3914 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3917 @code{const_double}.
3920 @code{const_double}.
3923 @code{const_double}.
3928 object.
3932 @code{define_constraint}. The remaining two definition expressions
3934 by @code{reload} if they fail to match.
3941 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3945 register. The constraint letter @samp{Q} is defined to represent a
3946 memory address of this type. If @samp{Q} is defined with
3949 memory address into a base register if required. This is analogous to
3950 the way an @samp{o} constraint can handle any memory operand.
3953 @code{define_constraint}.
3960 with @var{X} a base register.
3964 predicates that work the same way. They are treated analogously to
3965 the generic @samp{p} constraint.
3968 @code{define_constraint}.
3974 for constraints that match only @code{const_int}s. This may change in
3975 the future. For the time being, constraints with these names must be
3990 that match @code{const_double}s or @code{const_int}s.
3993 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3996 that section. Also, in the future the compiler may use this to give
3998 causes a reload failure.
4002 the internals manual's version of the machine-specific constraint tables.
4003 Use this for constraints that should not appear in @code{asm} statements.
4011 implicitly via the constraint string in a @code{match_operand}. The
4012 generated file @file{tm_p.h} declares a few interfaces for working
4013 with machine-specific constraints. None of these interfaces work with
4014 the generic constraints described in @ref{Simple Constraints}. This
4015 may change in the future.
4017 @strong{Warning:} @file{tm_p.h} may declare other functions that
4018 operate on constraints, besides the ones documented here. Do not use
4019 those functions from machine-dependent code. They exist to implement
4021 the compiler still expect. They will change or disappear in the
4022 future.
4025 mangling scheme for referring to them from C@. Constraint names that
4026 do not contain angle brackets or underscores are left unchanged.
4028 each @samp{>} with @samp{_g}. Here are some examples:
4030 @c the @c's prevent double blank lines in the printed manual.
4046 a larger identifier).
4051 constraint. Functions that take an @code{enum constraint_num} as an
4052 argument expect one of these constants.
4054 Machine-independent constraints do not have associated constants.
4055 This may change in the future.
4061 constraint. These functions are only visible if @file{rtl.h} was included
4062 before @file{tm_p.h}.
4067 constraint to test is given as an argument, @var{c}. If @var{c}
4069 @code{false}.
4073 Returns the register class associated with @var{c}. If @var{c} is not
4075 currently selected subtarget, returns @code{NO_REGS}.
4078 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4081 they must be tested in the C condition. In the example, the
4083 @samp{K} constraint. (This is a simplified version of a peephole
4084 definition from the i386 machine description.)
4108 generation pass of the compiler. Giving one of these names to an
4110 pattern to accomplish a certain task.
4115 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4117 1 to operand 0. For example, @samp{movsi} moves full-word data.
4122 to mode @var{m}. Bits outside of @var{m}, but which are within the
4123 same target word as the @code{subreg} are undefined. Bits which are
4124 outside the target word are left unchanged.
4126 This class of patterns is special in several ways. First of all, each
4128 because there is no other way to copy a datum from one place to another.
4130 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4132 Second, these patterns are not used solely in the RTL generation pass.
4134 slots into temporary registers. When it does so, one of the operands is
4136 into a register.
4141 registers other than the operands. For example, if you support the
4144 function which might generate new pseudo registers.
4148 some temporary registers.
4152 as an operand. Such an address will be replaced with a valid address
4153 later in the reload pass. In this case, nothing may be done with the
4154 address except to use it as it stands. If it is copied, it will not be
4155 replaced with a valid address. No attempt should be made to make such
4157 @code{change_address}) that will do so may be called. Note that
4158 @code{general_operand} will fail when applied to such an address.
4163 handling is required.
4168 machines explicit memory references will get optional reloads.
4171 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4174 you must provide an appropriate secondary_reload target hook.
4178 is unsafe to create new pseudo registers. If this variable is nonzero, then
4179 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4185 of 2.
4191 point members.
4194 instructions in and out of floating point registers. Unfortunately, I
4196 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4199 reload into a floating point register.
4206 @code{secondary_reload}.
4209 move between operand 0 and operand 1. Operand 2 describes the scratch
4210 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4211 macro in @pxref{Register Classes}.
4214 used in these patterns. First, only the predicate for the reload
4215 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4216 the predicates for operand 0 or 2. Second, there may be only one
4217 alternative in the constraints. Third, only a single register class
4219 are ignored. As a special exception, an empty constraint string
4220 matches the @code{ALL_REGS} register class. This may relieve ports
4222 for these patterns.
4229 any of the register except the part which belongs to mode @var{m}.
4234 from a memory address that is not naturally aligned for its mode.
4236 will be in operand 1. The other operand is guaranteed not to be a
4237 memory, so that it's easy to tell whether this is a load or store.
4240 @code{MISALIGNED_INDIRECT_REF} expression.
4244 Load several consecutive memory locations into consecutive registers.
4247 number of consecutive registers.
4251 registers from memory is to do them one at a time.
4255 ending register numbers or only a range of valid counts. For those
4257 and make the pattern fail if the restrictions are not met.
4261 also need @code{use} or @code{clobber} elements). Use a
4262 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4263 @file{rs6000.md} for examples of the use of this insn pattern.
4268 into consecutive memory locations. Operand 0 is the first of the
4270 operand 2 is a constant: the number of consecutive registers.
4275 into register operand 0. Both operands have mode @var{m}. The register
4278 of elements. The operation is equivalent to:
4288 from memory into a register of mode @samp{TI}@. The register
4289 contains two consecutive vectors of mode @samp{V4HI}@.
4295 is true. GCC assumes that, if a target supports this kind of
4297 loads for vectors of mode @var{n}.
4302 and register operands reversed. That is, the instruction is
4312 for a memory operand 0 and register operand 1.
4316 Set given field in the vector value. Operand 0 is the vector to modify,
4317 operand 1 is new value of field and operand 2 specify the field index.
4321 Extract given field from the vector value. Operand 1 is the vector, operand 2
4322 specify field index and operand 0 place to store value into.
4326 Initialize the vector to given values. Operand 0 is the vector to initialize
4327 and operand 1 is parallel containing values for individual fields.
4331 Output a conditional vector move. Operand 0 is the destination to
4334 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4335 modes @var{m} and @var{n} should have the same size. Operand 0
4338 comparison with a truth value of all-ones and a false value of all-zeros.
4342 Output a (variable) vector permutation. Operand 0 is the destination
4344 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4345 vector of the same width and number of elements as mode @var{m}.
4348 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4349 be computed modulo @math{2*@var{N}}. Note that if
4351 with just operand 1 and selector elements modulo @var{N}.
4357 mode @var{q}.
4362 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4365 but can efficiently perform a constant permutation. Further, the
4368 pattern is never expanded without @code{vec_perm_ok} returning true.
4372 the operation with, say, the vector constant loaded into a register.
4376 Output a push instruction. Operand 0 is value to push. Used only when
4377 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4379 @code{MEM} expression forming the push operation. The @code{mov} expander
4380 method is deprecated.
4384 Add operand 2 and operand 1, storing the result in operand 0. All operands
4385 must have mode @var{m}. This can be used even on two-address machines, by
4386 means of constraints requiring operands 1 and 0 to be the same location.
4415 Similar, for other arithmetic operations.
4420 result in operand 0. All operands must have mode @var{m}. This
4422 @code{fmal} builtin functions from the ISO C99 standard. The
4425 rounding step between the operations.
4430 product instead of added to the product. This is represented
4440 is negated before being added to operand 3. This is represented
4450 is negated before subtracting operand 3. This is represented
4460 Signed minimum and maximum operations. When used with floating point,
4461 if both operands are zeros, or if either operand is @code{NaN}, then
4462 it is unspecified which of the two operands is returned as the result.
4467 Find the signed minimum/maximum of the elements of a vector. The vector is
4469 operand 0 (also a vector). The output and input vector should have the same
4470 modes.
4475 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4477 operand 0 (also a vector). The output and input vector should have the same
4478 modes.
4482 Compute the sum of the signed elements of a vector. The vector is operand 1,
4484 (also a vector). The output and input vector should have the same modes.
4488 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4490 (also a vector). The output and input vector should have the same modes.
4496 Compute the sum of the products of two signed/unsigned elements.
4497 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4498 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4499 wider than the mode of the product. The result is placed in operand 0, which
4500 is of the same mode as operand 3.
4507 operand 1. Add operand 1 to operand 2 and place the widened result in
4508 operand 0. (This is used express accumulation of elements into an accumulator
4509 of a wider mode.)
4514 Whole vector left/right shift in bits.
4515 Operand 1 is a vector to be shifted.
4516 Operand 2 is an integer shift amount in bits.
4517 Operand 0 is where the resulting shifted vector is stored.
4518 The output and input vectors should have the same modes.
4522 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4524 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4525 size N/2 are concatenated after narrowing them down using truncation.
4530 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4531 are vectors of the same mode having N integral elements of size S.
4534 saturating arithmetic.
4540 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4541 floating point elements of size S@. Operand 0 is the resulting vector
4542 in which 2*N elements of size N/2 are concatenated.
4548 integral or floating point elements. The input vector (operand 1) has N
4549 elements of size S@. Widen (promote) the high/low elements of the vector
4551 values of size 2*S in the output vector (operand 0).
4557 integral elements. The input vector (operand 1) has N elements of size S.
4559 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4568 vector of signed/unsigned integral elements. The input vector (operand 1)
4569 has N elements of size S@. Convert the high/low elements of the vector using
4571 the output vector (operand 0).
4579 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4580 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4582 output vector (operand 0).
4590 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4591 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4593 output vector (operand 0).
4598 a @code{SImode} product in operand 0.
4603 Similar widening-multiplication instructions of other widths.
4610 multiplication.
4618 multiplication.
4623 @var{m}, and store the most significant half of the product in operand 0.
4624 The least significant half of the product is discarded.
4628 Similar, but the multiplication is unsigned.
4633 operand 3, and store the result in operand 0. Operands 1 and 2
4634 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4636 the size of @var{m}.
4639 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4641 These instructions are not allowed to @code{FAIL}.
4646 operands instead of sign-extending them.
4651 signed-saturating.
4656 unsigned-saturating.
4661 result from operand 3, and store the result in operand 0. Operands 1 and 2
4662 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4664 the size of @var{m}.
4668 from operand 3.
4670 These instructions are not allowed to @code{FAIL}.
4675 operands instead of sign-extending them.
4680 signed-saturating.
4685 unsigned-saturating.
4689 Signed division that produces both a quotient and a remainder.
4691 in operand 0 and a remainder stored in operand 3.
4695 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4697 and remainder are computed.
4703 quotient or remainder and generate the appropriate instruction.
4707 Similar, but does unsigned division.
4715 2, and store the result in operand 0. Here @var{m} is the mode of
4718 mode before generating the instruction. The meaning of out-of-range shift
4719 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4720 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4728 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4737 instead of a scalar type.
4743 Negate operand 1 and store the result in operand 0.
4747 Store the absolute value of operand 1 into operand 0.
4751 Store the square root of operand 1 into operand 0.
4756 type @code{float}.
4761 operand 0, rounded towards zero to an integer.
4766 type @code{float}.
4771 operand 0, rounded to the nearest integer.
4776 to the C data type @code{float}.
4780 Store the cosine of operand 1 into operand 0.
4785 type @code{float}.
4789 Store the sine of operand 1 into operand 0.
4794 type @code{float}.
4798 Store the exponential of operand 1 into operand 0.
4803 type @code{float}.
4807 Store the natural logarithm of operand 1 into operand 0.
4812 type @code{float}.
4817 into operand 0.
4822 type @code{float}.
4828 determine the quadrant of the result.
4833 type @code{float}.
4837 Store the largest integral value not greater than argument.
4842 type @code{float}.
4846 Store the argument rounded to integer towards zero.
4851 type @code{float}.
4855 Store the argument rounded to integer away from zero.
4860 type @code{float}.
4864 Store the argument rounded to integer away from zero.
4869 type @code{float}.
4878 type @code{float}.
4889 type @code{float}.
4895 rounding mode and store in operand 0 (which has mode @var{n}).
4901 from zero and store in operand 0 (which has mode @var{n}).
4907 operand 0 (which has mode @var{n}).
4913 operand 0 (which has mode @var{n}).
4918 2 into operand 0.
4923 type @code{float}.
4928 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4931 generating the instruction.
4934 corresponds to the C data type @code{int}.
4939 at the most significant bit position. If @var{x} is 0, the
4941 the result is undefined or has a useful value.
4944 operand to that mode before generating the instruction.
4949 at the least significant bit position. If @var{x} is 0, the
4951 the result is undefined or has a useful value.
4954 operand to that mode before generating the instruction.
4958 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4961 generating the instruction.
4965 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4966 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4968 the operand to that mode before generating the instruction.
4972 Store the bitwise-complement of operand 1 into operand 0.
4976 Block move instruction. The destination and source blocks of memory
4978 address in mode @code{Pmode}.
4980 The number of bytes to move is the third operand, in mode @var{m}.
4981 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4985 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4986 that appear negative) and also a pattern with @code{word_mode}.
4989 destination, in the form of a @code{const_int} rtx. Thus, if the
4991 it may provide the value 4 for this operand.
4994 respectively. The expected alignment differs from alignment in operand 4
4996 all cases. This expected alignment is also in bytes, just like operand 4.
4997 Expected size, when unknown, is set to @code{(const_int -1)}.
5001 on their first, second and fourth operands. Note that the mode @var{m}
5003 individually moved data units in the block.
5006 that the source and destination strings might overlap.
5010 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5011 an output operand in mode @code{Pmode}. The addresses of the
5013 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5015 which the @code{NUL} terminator was stored in the destination string.
5019 Block set instruction. The destination string is the first operand,
5020 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5021 number of bytes to set is the second operand, in mode @var{m}. The value to
5022 initialize the memory with is the third operand. Targets that only support the
5023 clearing of memory should reject any value that is not the constant 0. See
5024 @samp{movmem@var{m}} for a discussion of the choice of mode.
5027 of a @code{const_int} rtx. Thus, if the compiler knows that the
5029 operand.
5032 respectively. The expected alignment differs from alignment in operand 4
5034 all cases. This expected alignment is also in bytes, just like operand 4.
5035 Expected size, when unknown, is set to @code{(const_int -1)}.
5037 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5041 String compare instruction, with five operands. Operand 0 is the output;
5042 it has mode @var{m}. The remaining four operands are like the operands
5043 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5045 string. The instruction is not allowed to prefetch more than one byte
5047 that may access an invalid page or segment and cause a fault. The
5049 they are equal to zero. The effect of the instruction is to store a
5050 value in operand 0 whose sign indicates the result of the comparison.
5054 String compare instruction, without known maximum length. Operand 0 is the
5055 output; it has mode @var{m}. The second and third operand are the blocks of
5057 @code{Pmode}.
5060 destination, in the form of a @code{const_int} rtx. Thus, if the
5062 it may provide the value 4 for this operand.
5065 order starting at the beginning of each string. The instruction is not allowed
5068 cause a fault. The comparison will terminate when the fetched bytes
5069 are different or if they are equal to zero. The effect of the
5071 result of the comparison.
5076 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5078 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5079 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5080 the comparison will not stop if both bytes are zero. The effect of
5082 the result of the comparison.
5086 Compute the length of a string, with three operands.
5091 of the beginning of the string.
5097 @var{n}).
5103 @var{n}).
5109 has mode @var{n}). This instruction's result is defined only when
5110 the value of operand 1 is an integer.
5113 define the @code{ftrunc} pattern.
5119 has mode @var{n}). This instruction's result is defined only when the
5120 value of operand 1 is an integer.
5126 store it in operand 0 (valid for floating point mode @var{m}).
5131 of mode @var{m} by converting the value to an integer.
5136 value of mode @var{m} by converting the value to an integer.
5141 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5142 point or both floating point.
5147 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5148 point or both floating point.
5153 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5154 point.
5159 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5162 or fixed-point to floating-point.
5163 When overflows or underflows happen, the results are undefined.
5168 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5170 or floating-point to fixed-point.
5172 results to the maximum or the minimum.
5177 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5179 fixed-point to unsigned integer.
5180 When overflows or underflows happen, the results are undefined.
5185 @var{n} and store in operand 0 (which has mode @var{n}).
5187 results to the maximum or the minimum.
5193 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5195 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5196 be valid for @code{word_mode}.
5199 for operands 2 and 3 and the constant is never zero for operand 2.
5202 before it is stored in operand 0.
5206 Like @samp{extv} except that the bit-field value is zero-extended.
5212 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5213 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5214 Operands 1 and 2 must be valid for @code{word_mode}.
5217 for operands 1 and 2 and the constant is never zero for operand 1.
5222 comparison in operand 1. If the comparison is true, operand 2 is moved
5223 into operand 0, otherwise operand 3 is moved.
5226 being moved. Some machines, sparc64 for example, have instructions that
5228 codes and vice versa.
5231 define these patterns.
5235 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5237 comparison in operand 1. If the comparison is true, operand 2 is moved into
5238 operand 0, otherwise (operand 2 + operand 3) is moved.
5243 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5244 are the first and second operand of the comparison, respectively.
5246 @code{match_operand} expression. The compiler automatically sees which
5247 mode you have used and supplies an operand of that mode.
5250 else must be negative. Otherwise the instruction is not suitable and
5251 you should omit it from the machine description. You describe to the
5253 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5256 onto the one you chose.
5261 allow these operands. Likewise if a given comparison operator will
5263 @code{ordered_comparison_operator} predicate is often useful in this case).
5267 around an assignment of zero to the target---or a libcall. If the predicate
5269 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5275 from the machine description.
5279 Conditional branch instruction combined with a compare instruction.
5280 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5281 first and second operands of the comparison, respectively. Operand 3
5282 is a @code{label_ref} that refers to the label to jump to.
5286 A jump inside a function; an unconditional branch. Operand 0 is the
5287 @code{label_ref} of the label to jump to. This pattern name is mandatory
5288 on all machines.
5292 Subroutine call instruction returning no value. Operand 0 is the
5295 operands.
5298 pattern. It is supplied for the sake of some RISC machines which need
5300 the RTL instead of operand 1.
5303 function. Note, however, that this address can be a @code{symbol_ref}
5305 target machine. If it is also not a valid argument for a call
5308 address into a register and uses that register in the call instruction.
5312 Subroutine call instruction returning a value. Operand 0 is the hard
5313 register in which the value is returned. There are three more
5315 instruction (but with numbers increased by one).
5318 insn.
5324 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5326 adjustment made to the frame pointer.
5330 can be eliminated, if desired.
5334 Subroutine call instruction returning a value of any type. Operand 0 is
5338 the saving of a function return value into the result block.
5343 returned. This instruction pattern is required on machines that have
5345 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5349 Subroutine return instruction. This instruction pattern name should be
5351 from a function.
5354 RTL generation phase. In this case it is to support machines where
5357 return. Normally, the applicable functions are those which do not need
5358 to save any registers or allocate stack space.
5361 @code{simple_return} if no epilogue is required.
5365 Subroutine return instruction. This instruction pattern name should be
5367 from a function on a path where no epilogue is required. This pattern
5371 any of the effects of the epilogue. Additional uses may be introduced on
5372 paths where both the prologue and the epilogue have executed.
5378 epilogue would only be a single instruction. For machines with register
5380 a register window push is required.
5398 named @samp{return} pattern.
5402 Untyped subroutine return instruction. This instruction pattern should
5404 instructions are needed to return a value of any type.
5409 the restoring of a function return value from the result block.
5413 No-op instruction. This instruction pattern name should always be defined
5414 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5415 RTL pattern.
5419 An instruction to jump to an address which is operand zero.
5420 This pattern name is mandatory on all machines.
5424 Instruction to jump through a dispatch table, including bounds checking.
5429 The index to dispatch on, which has mode @code{SImode}.
5432 The lower bound for indices in the table, an integer constant.
5436 minus the smallest one (both inclusive).
5439 A label that precedes the table itself.
5442 A label to jump to if the index has a value outside the bounds.
5446 @code{jump_insn}. The number of elements in the table is one plus the
5447 difference between the upper bound and the lower bound.
5451 Instruction to jump to a variable address. This is a low-level
5453 is no @samp{casesi} pattern.
5456 which should immediately precede the jump table. If the macro
5459 it is an absolute address to jump to. In either case, the first operand has
5460 mode @code{Pmode}.
5463 table it uses. Its assembler code normally has no need to use the
5465 that the jump optimizer will not delete the table as unreachable code.
5471 jumps if the register is nonzero. Operand 0 is the register to
5473 register is nonzero. @xref{Looping Patterns}.
5477 reduction is enabled.
5482 the register is nonzero. This instruction takes five operands: Operand
5488 1); operand 4 is the label to jump to if the register is nonzero.
5489 @xref{Looping Patterns}.
5493 modify suitable loops to utilize it. If nested low-overhead looping is
5495 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5497 too large for this instruction, make it fail.
5503 used by a low-overhead looping instruction. If initialization insns do
5505 (@pxref{Expander Definitions}) and make it fail.
5511 into operand 0.
5515 and also has mode @code{Pmode}.
5519 pointer were used in an indirect call.
5523 used in an indirect call.
5538 from an object of mode @code{Pmode}. Do not define these patterns on
5539 such machines.
5542 restores. On those machines, define the patterns corresponding to the
5544 Definitions}) that produces the required insns. The three types of
5551 restores the stack pointer when the block is exited.
5556 function allocates variable-sized objects or calls @code{alloca}. Only
5558 restore sequence on some machines.
5562 branched to by nested functions. It saves the stack pointer in such a
5564 restore the stack pointer. The compiler generates code to restore the
5567 stack backchains. Place insns in these patterns to save and restore any
5568 such required data.
5572 is the stack pointer. The mode used to allocate the save area defaults
5574 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5577 because a machine-specific save area can be used). Operand 0 is the
5578 stack pointer and operand 1 is the save area for restore operations. If
5580 @code{VOIDmode} since these saves can be arbitrarily nested.
5584 nonlocal gotos and a @code{reg} in the other two cases.
5589 the stack pointer to create space for dynamically allocated data.
5591 Store the resultant pointer to this space into operand 0. If you
5593 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5595 location of the space to operand 0. In the latter case, you must
5597 stack is free.
5599 Do not define this pattern if all that must be done is the subtraction.
5601 maintaining the back chain. Define this pattern to emit those
5602 operations in addition to updating the stack pointer.
5608 an error if the stack has overflowed. The single operand is the address in
5609 the stack farthest from the current stack pointer that you need to validate.
5611 stack limit from a global or thread-specific variable or register.
5618 error if the stack has overflowed. The single operand is the memory reference
5619 in the stack that needs to be probed.
5623 Emit code to generate a non-local goto, e.g., a jump from one function
5624 to a label in an outer function. This pattern has four arguments,
5625 each representing a value to be used in the jump. The first
5630 location for the incoming static chain.
5636 to the dispatcher. You need only define this pattern if this code will
5637 not work on your machine.
5642 nonlocal goto after the code already generated by GCC@. You will not
5643 normally need to define this pattern. A typical reason why you might
5645 must be restored when the frame pointer is restored. Note that a nonlocal
5647 that is shared by all functions of a given module need not be restored.
5648 There are no arguments.
5653 exception handler that isn't needed at the site of a nonlocal goto. You
5654 will not normally need to define this pattern. A typical reason why you
5657 an exception. There are no arguments.
5662 the @code{jmp_buf}. You will not normally need to define this pattern.
5664 as a pointer to a global table, must be restored. Though it is
5666 address of a label for instance). The single argument is a pointer to
5667 the @code{jmp_buf}. Note that the buffer is five words long and that
5668 the first three are normally used by the generic mechanism.
5673 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5674 will not normally need to define this pattern. A typical reason why you
5676 table, must be restored. It takes one argument, which is the label
5678 at a small offset from that label.
5682 This pattern, if defined, performs the entire action of the longjmp.
5684 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5685 @code{jmp_buf}.
5691 built. It is intended to handle non-trivial actions needed along
5692 the abnormal return path.
5695 is passed as operand to this pattern. It will normally need to copied by
5696 the pattern to some special register or memory location.
5699 if defined; it will have already been assigned.
5702 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5704 handling is to be used.
5709 This pattern, if defined, emits RTL for entry to a function. The function
5711 pointer register, saving callee saved registers, etc.
5714 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5717 instruction scheduling.
5722 This pattern, if defined, emits RTL for a register window save. It should
5724 are decoupled from calls to subroutines. The canonical example is the SPARC
5725 architecture.
5730 This pattern emits RTL for exit from a function. The function
5732 registers and emitting the return instruction.
5735 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5738 instruction scheduling or which have delay slots for their return instruction.
5743 branch back to the calling function. This pattern will be emitted before any
5744 sibling call (aka tail call) sites.
5748 function.
5753 kind of signal to be raised. Among other places, it is used by the Java
5754 front end to signal `invalid array index' exceptions.
5758 Conditional trap instruction. Operand 0 is a piece of RTL which
5760 comparison. Operand 3 is the trap code, an integer.
5778 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5780 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5785 respectively, a low or moderate degree of temporal locality.
5788 the values of operands 1 and 2.
5795 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5802 before the instruction with respect to loads and stores after the instruction.
5803 This pattern has no operands.
5809 operation. Operand 1 is the memory on which the atomic operation is
5810 performed. Operand 2 is the ``old'' value to be compared against the
5811 current contents of the memory location. Operand 3 is the ``new'' value
5812 to store in the memory if the compare succeeds. Operand 0 is the result
5814 before the operation. If the compare succeeds, this should obviously be
5815 a copy of operand 2.
5817 This pattern must show that both operand 0 and operand 1 are modified.
5822 after the atomic operation.
5827 branch or store-flag operation immediately after the compare-and-swap.
5831 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5834 operand of the comparison (the second will be @code{(const_int 0)}).
5839 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
5842 @code{init_sync_libfuncs}.
5845 interruptable locking.
5857 These patterns emit code for an atomic operation on memory.
5858 Operand 0 is the memory on which the atomic operation is performed.
5859 Operand 1 is the second operand to the binary operator.
5864 after the atomic operation.
5867 from a compare-and-swap operation, if defined.
5880 and return the value that the memory contained before the operation.
5883 to the binary operator.
5888 after the atomic operation.
5891 from a compare-and-swap operation, if defined.
5905 after the operation, rather than before the operation.
5910 This pattern takes two forms, based on the capabilities of the target.
5913 is the value to set in the lock.
5917 operand, and the value operand is stored in the memory operand.
5920 should be rejected with @code{FAIL}. In this case the target may use
5921 an atomic test-and-set bit operation. The result operand should contain
5922 1 if the bit was previously set and 0 if the bit was previously clear.
5923 The true contents of the memory operand are implementation defined.
5927 operations after the pattern do not occur until the lock is acquired.
5930 a compare-and-swap operation, if defined.
5936 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5937 that contains the lock; operand 1 is the value to store in the lock.
5942 of the memory operand are implementation defined.
5946 released only after all previous memory operations have completed.
5949 will be emitted, followed by a store of the value to the memory operand.
5954 operation with memory model semantics. Operand 2 is the memory on which
5955 the atomic operation is performed. Operand 0 is an output operand which
5956 is set to true or false based on whether the operation succeeded. Operand
5958 the operation was attempted. Operand 3 is the value that is expected to
5959 be in memory. Operand 4 is the value to put in memory if the expected
5960 value is found there. Operand 5 is set to 1 if this compare and swap is to
5961 be treated as a weak operation. Operand 6 is the memory model to be used
5962 if the operation is a success. Operand 7 is the memory model to be used
5963 if the operation fails.
5967 the memory model in operand 6 is issued.
5970 then fencing based on the memory model in operand 7 is issued.
5974 ignored. Note a strong implementation must be provided.
5978 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
5983 semantics. Operand 1 is the memory address being loaded from. Operand 0
5984 is the result of the load. Operand 2 is the memory model to be used for
5985 the load operation.
5989 operation if a normal load would not be atomic.
5994 semantics. Operand 0 is the memory address being stored to. Operand 1
5995 is the value to be written. Operand 2 is the memory model to be used for
5996 the operation.
5999 perform a normal store and surround it with any required memory fences. If
6001 attempted with the result being ignored.
6006 semantics. Operand 1 is the memory location the operation is performed on.
6008 in the memory pointed to by operand 1. Operand 2 is the value to be
6009 stored. Operand 3 is the memory model to be used.
6013 compare and swap loop.
6026 model semantics. Operand 0 is the memory on which the atomic operation is
6027 performed. Operand 1 is the second operand to the binary operator.
6028 Operand 2 is the memory model to be used by the operation.
6031 @code{sync} patterns, or equivilent patterns which return a result. If
6032 none of these are available a compare-and-swap loop will be used.
6045 model semantics, and return the original value. Operand 0 is an output
6047 operation was performed. Operand 1 is the memory on which the atomic
6048 operation is performed. Operand 2 is the second operand to the binary
6049 operator. Operand 3 is the memory model to be used by the operation.
6052 @code{sync} patterns. If none of these are available a compare-and-swap
6053 loop will be used.
6066 model semantics and return the result after the operation is performed.
6068 operation. Operand 1 is the memory on which the atomic operation is
6069 performed. Operand 2 is the second operand to the binary operator.
6070 Operand 3 is the memory model to be used by the operation.
6075 result. If none of these are available a compare-and-swap loop will be
6076 used.
6081 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6083 previous contents of the byte was "set", and false otherwise. Operand 1
6084 is the @code{QImode} memory to be modified. Operand 2 is the memory
6085 model to be used.
6089 instruction.
6094 memory model semantics. Operand 0 is the memory model to be used.
6098 barrier pattern.
6103 memory model semantics. Operand 0 is the memory model to be used.
6107 instructions.
6111 barrier pattern.
6118 a register afterward. This is to avoid leaking the value some place
6120 having clobbered it.
6122 If this pattern is not defined, then a plain move pattern is generated.
6130 weren't equal.
6133 conditional branch pattern is used.
6139 memory. The region is bounded to by the Pmode pointers in operand 0
6140 inclusive and operand 1 exclusive.
6143 @code{__clear_cache} is used.
6150 @c configuration in older tetex distributions. Known to not work:
6151 @c tetex-1.0.7, known to work: tetex-2.0.2.
6158 Sometimes an insn can match more than one instruction pattern. Then the
6159 pattern that appears first in the machine description is the one used.
6162 do match) should usually go first in the description.
6165 a pattern when it is not valid. For example, the 68000 has an
6167 for converting a byte to floating point. An instruction converting
6168 an integer to floating point could match either one. We put the
6170 be used rather than the other. (Otherwise a large integer might
6171 be generated as a single-byte immediate quantity, which would not work.)
6174 constant value.
6184 machine mode of one or more operands. For example, there may be
6198 extend a constant value could match either pattern. The pattern it
6199 actually will match is the one that appears first in the file. For correct
6201 here). If the pattern matches the @code{QImode} instruction, the results
6202 will be incorrect if the constant value does not actually fit that mode.
6206 compilations.
6210 cases. Similarly for memory references. Because of this substitution,
6212 instructions. Instead, they should be generated from the same pattern
6214 generating the appropriate machine instruction.
6223 GCC does not assume anything about how the machine realizes jumps.
6225 a @code{define_expand}, which expands to all the required insns.
6229 or not according to its value. For many machines, however,
6231 more flexible approach with one @code{define_expand} is used in GCC.
6233 have compare-and-branch instructions but no condition code. It also
6235 by different kinds of conditional branches (e.g. integer vs. floating-point),
6236 or by conditional branches with respect to conditional stores.
6241 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6243 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6246 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6254 one set of conditional branch instructions as in the PowerPC.
6264 make loops more efficient. A common example is the 68000 @samp{dbra}
6266 result was greater than zero. Other machines, in particular digital
6268 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6271 iterations. This avoids the need for fetching and executing a
6273 the jump.
6275 GCC has three special named patterns to support low overhead looping.
6277 and @samp{doloop_end}. The first pattern,
6279 generation but may be emitted during the instruction combination phase.
6282 zero. Some targets also require the loop optimizer to add a
6284 positive. This is needed if the target performs a signed loop
6285 termination test. For example, the 68000 uses a pattern similar to the
6307 deal with its own reloads, hence the `m' constraints. Also note that
6311 decrement operation, in this case @minus{}1. Note that the following similar
6312 pattern will not be matched by the combiner.
6334 information collected during strength reduction.
6339 needed for some low-overhead looping instructions.
6342 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6344 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6345 emitted at the end of the loop. The machine dependent reorg pass checks
6348 there are no instructions in the loop which would cause problems). Any
6349 additional labels can be emitted at this point. In addition, if the
6352 instruction pair.
6357 register for the latter as an iteration counter. This pseudo register
6358 cannot be used within the loop (i.e., general induction variables cannot
6360 may become redundant and removed by the flow pass.
6371 operation performed by a single machine instruction. This situation is
6373 instructions. In such cases, the compiler attempts to convert these
6375 number of insn patterns required.
6383 second operand. If a machine only supports a constant as the second
6385 be supplied.
6390 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6393 floating-point.
6403 first operand.
6408 the operations as far as possible. For instance,
6411 @code{(minus A (mult B C))}.
6416 if the first argument is a condition code register or @code{(cc0)}.
6421 above.
6425 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6426 of @code{ltu}.
6430 @code{(plus @var{x} (const_int @var{-n}))}.
6433 Within address computations (i.e., inside @code{mem}), a left shift is
6434 converted into the appropriate multiplication by a power of two.
6441 logical-and or logical-or operation. If this results in only one
6442 operand being a @code{not} expression, it will be the first one.
6470 logically equivalent RTL expressions.
6476 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6491 @code{and} or @code{sign_extract} operations.
6498 for @code{zero_extend}.
6505 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6506 operand of @code{mult} is also a shift, then that is extended also.
6508 original operation had sufficient precision to prevent overflow.
6513 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6525 represent them. For these target machines, you can write a
6526 @code{define_expand} to specify how to generate the sequence of RTL@.
6531 only for RTL generation and it can produce more than one RTL insn.
6537 The name. Each @code{define_expand} must have a name, since the only
6538 use for it is to refer to it by name.
6541 The RTL template. This is a vector of RTL expressions representing
6542 a sequence of separate instructions. Unlike @code{define_insn}, there
6543 is no implicit surrounding @code{PARALLEL}.
6546 The condition, a string containing a C expression. This expression is
6549 is run. This is just like the condition of a @code{define_insn} that
6550 has a standard name. Therefore, the condition (if present) may not
6552 target-machine-type flags. The compiler needs to test these conditions
6554 are available in a particular run.
6559 the RTL template.
6563 insns directly by calling routines such as @code{emit_insn}, etc.
6564 Any such insns precede the ones that come from the RTL template.
6568 @code{define_insn} in the machine description. Otherwise, the compiler
6570 it.
6574 is used. In particular, it gives a predicate for each operand.
6578 occurrence in the RTL template. This enters information on the operand's
6579 predicate into the tables that record such things. GCC uses the
6581 valid RTL code. If the operand is referred to more than once, subsequent
6582 references should use @code{match_dup}.
6586 @code{define_expand}. Internal operands are substituted into the RTL
6587 template with @code{match_dup}, never with @code{match_operand}. The
6589 compiler when it requests use of this pattern. Instead, they are computed
6590 within the pattern, in the preparation statements. These statements
6592 @code{operands} so that @code{match_dup} can find them.
6595 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6596 as a statement.
6602 Use the @code{DONE} macro to end RTL generation for the pattern. The
6605 preparation statements; the RTL template will not be generated.
6609 Make the pattern fail on this occasion. When a pattern fails, it means
6610 that the pattern was not truly available. The calling routines in the
6611 compiler will try other strategies for code generation using other patterns.
6614 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
6615 operations.
6621 insn.
6624 initial insn list. If the preparation statement always invokes
6674 fail in other cases where machine insns aren't available. When it fails,
6676 library call).
6680 @code{define_insn} in that case. Here is another case (zero-extension
6699 and the other to copy the input operand into its low half. This sequence
6701 operand, so the preparation statement makes sure this isn't so. The
6703 temporary register if it refers to @code{operands[0]}. It does this
6704 by emitting another RTL insn.
6706 Finally, a third example shows the use of an internal operand.
6708 against a halfword mask. But this mask cannot be represented by a
6710 on this machine. So it must be copied into a register with
6711 @code{force_reg} and then the register used in the @code{and}.
6728 @code{barrier} or @code{note}. It must be an @code{insn},
6729 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
6731 itself. Such an insn will generate no code, but it can avoid problems
6732 in the compiler.
6743 into multiple insns. On machines that have instructions requiring
6747 be able to move insns into one-instruction delay slots. However, some
6748 insns may generate more than one machine instruction. These insns
6749 cannot be placed into a delay slot.
6752 each corresponding to one machine instruction. The disadvantage of
6754 more space. If the resulting insns are too complex, it may also
6755 suppress some optimizations. The compiler splits the insn if there is a
6757 scheduling.
6759 The insn combiner phase also splits putative insns. If three insns are
6762 the complex pattern into two insns that are recognized. Usually it can
6764 subexpression. However, in some other cases, such as performing an
6766 split the addition into two insns is machine-dependent.
6770 complex insn into several simpler insns. It looks like this:
6784 @code{define_insn}. When an insn matching @var{insn-pattern} and
6787 @var{new-insn-pattern-2}, etc.
6792 generated code or emit some insns whose pattern is not fixed. Unlike
6794 generate any new pseudo-registers. Once reload has completed, they also
6795 must not allocate any space in the stack frame.
6798 circumstances. If an insn needs to be split for delay slot scheduling
6802 of that @code{define_insn}. In that case, the new insn patterns must
6805 of those definitions.
6808 example from @file{a29k.md}, which splits a @code{sign_extend} from
6827 case that the pattern is @emph{not} matched by any @code{define_insn}.
6831 register. In these cases, the combiner expects exactly two new insn
6832 patterns to be generated. It will verify that these patterns match some
6835 @code{define_split} that will never produce insns that match).
6838 @file{rs6000.md}:
6863 insn. The add with the smaller displacement is written so that it
6864 can be substituted into the address of a subsequent operation.
6883 looks like sign-extended to 16 bits. Then see what constant
6884 could be XOR'ed with C to get the sign-extended value.} */
6897 insns that don't. Instead, write two separate @code{define_split}
6899 are not valid.
6902 jumps or create new jumps in while splitting non-jump instructions. As
6904 several restriction apply.
6908 jump. When new sequence contains multiple jump instructions or new labels,
6909 more assistance is needed. Splitter is required to create only unconditional
6910 jumps, or simple conditional jump instructions. Additionally it must attach a
6911 @code{REG_BR_PROB} note to each conditional jump. A global variable
6913 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6915 forward jumps to the newly created labels.
6919 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6937 @var{insn-attributes} are used as in @code{define_insn}. The
6939 in a @code{define_split}. The @var{split-condition} is also used as in
6942 logical ``and'' of the split condition with the insn condition. For example,
6943 from i386.md:
6962 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6966 patterns. It exists for compactness, and as a maintenance tool to prevent
6967 having to ensure the two patterns' templates match.
6972 @section Including Patterns in Machine Descriptions.
6978 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6997 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6998 directory @file{gcc/config/target} is regarded as the default directory.
7002 and placed into subdirectories.
7012 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7020 is permitted but is not encouraged.
7023 @cindex directory options .md
7027 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7032 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7038 searched for header files. This can be used to override a system machine definition
7040 searched before the default machine description file directories. If you use more than
7042 order; the standard default directory come after.
7053 definitions of machine-specific peephole optimizations.
7056 flow in the program does not suggest that it should try them. For example,
7059 first one. A machine-specific peephole optimizer can detect such
7060 opportunities.
7062 There are two forms of peephole definitions that may be used. The
7064 match insns and substitute assembly text. Use of @code{define_peephole}
7065 is deprecated.
7068 insns. The @code{peephole2} pass is run after register allocation
7070 targets that do scheduling.
7098 machine-specific information in this machine description. If present,
7099 it must obey the same rules as in a @code{define_insn}.
7102 consecutive insns. The optimization applies to a sequence of insns when
7104 the next, and so on.
7107 @code{define_insn}. Peepholes are checked only at the last stage just
7108 before code generation, and only optionally. Therefore, any insn which
7111 stages.
7114 @code{match_operator}, and @code{match_dup}, as usual. What is not
7116 definition. So, you can check for identical operands in two insns by
7118 other.
7123 to apply whenever the peephole matches. If the peephole matches
7124 but the constraints are not satisfied, the compiler will crash.
7128 previously tested.
7131 checked. This is a C expression which makes the final decision whether to
7132 perform the optimization (we do so if the expression is nonzero). If
7135 patterns.
7138 is complete. Therefore, the peephole definition can check which
7140 the operands.
7145 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7147 @code{prev_active_insn} to find the preceding insns.
7152 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7156 value (from @code{operands[@var{i}]}).
7159 new insn. The @var{template} controls ultimate output of assembler code
7160 for this combined insn. It works exactly like the template of a
7161 @code{define_insn}. Operand numbers in this template are the same ones
7162 used in matching the original sequence of insns.
7166 opportunity to match them. The peephole optimizer definition itself serves
7167 as the insn pattern to control how the insn is output.
7170 so the insns they produce are never combined or rearranged in any way.
7184 output_asm_insn ("move.l %1,(sp)", xoperands);
7185 output_asm_insn ("move.l %1,-(sp)", operands);
7186 return "fmove.d (sp)+,%0";
7224 condition codes are represented in an unusual manner. The compiler
7227 peephole optimizations. So it is up to you to alter the assembler code
7228 that the peephole produces. Supply C code to write the assembler output,
7230 assembler code as appropriate.
7234 operand of @code{define_insn}. There is one important difference: the
7236 enclosed in square brackets. Usually, there is only one: then the same
7237 action can be written as an element of a @code{define_peephole}. But
7239 implicitly enclosed in a @code{parallel}. Then you must explicitly
7241 @code{define_peephole}. Thus, if an insn pattern looks like this,
7251 "divsl%.l %2,%3:%0")
7279 lifetimes must be.
7295 single instruction, but a sequence of instructions.
7298 output template. If appropriate registers are not free, the pattern
7299 will simply not match.
7304 the top level of the input pattern. The allocated register (initially) will
7305 be dead at the point requested within the original sequence. If the scratch
7308 at which the register must be available.
7330 able to schedule around the memory load latency. It allocates a single
7332 to be live only at the point just before the arithmetic.
7355 beginning of the sequence is killed by the first or second @code{set}.
7366 values for each. Every generated insn is assigned a value for each attribute.
7368 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7369 to track the condition codes.
7372 * Defining Attributes:: Specifying attributes and their values.
7373 * Expressions:: Valid expressions for attribute values.
7374 * Tagging Insns:: Assigning attribute values to insns.
7375 * Attr Example:: An example of assigning attributes.
7376 * Insn Lengths:: Computing the length of insns.
7377 * Constant Attributes:: Defining attributes that are constant.
7378 * Delay Slots:: Defining delay slots required for a machine.
7379 * Processor pipeline description:: Specifying information for insn scheduling.
7391 by the target machine. It looks like:
7397 @var{name} is a string specifying the name of the attribute being defined.
7398 Some attributes are used in a special way by the rest of the compiler. The
7400 insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
7403 conditional variants of instruction patterns. The compiler internally uses
7405 used elsewhere as alternative names.
7409 indicate that the attribute takes numeric values.
7413 an explicit value for this attribute. @xref{Attr Example}, for more
7414 information on the handling of defaults. @xref{Constant Attributes},
7415 for information on attributes that do not depend on any particular insn.
7417 @findex insn-attr.h
7419 @file{insn-attr.h} file. For cases where an explicit set of values is
7424 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7429 the attribute name and value are first converted to uppercase.
7433 returns the attribute value for that insn.
7443 the following lines will be written to the file @file{insn-attr.h}.
7454 @code{int}.
7456 There are attributes which are tied to a specific meaning. These
7462 code chunks. This is especially important when verifying branch
7463 distances. @xref{Insn Lengths}.
7468 generation. @xref{Disable Insn Alternatives}.
7481 @var{enum} (@pxref{define_enum}). This form allows you to use
7483 repeat the list each time. For example:
7506 but without duplicating the processor list. The second example defines two
7508 defines a single C enum (@code{processor}).
7516 plus a few specific to attribute definitions, to be discussed below.
7522 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7523 must be non-negative.
7529 overrides on specific instructions (@pxref{Tagging Insns}).
7533 The string @var{value} specifies a constant attribute value.
7535 the attribute is to be used for the insn containing this expression.
7537 of a @code{define_attr}.
7541 @code{const_int} would be used in this case). Otherwise, it must
7542 contain one of the valid values for the attribute.
7546 @var{test} specifies an attribute test, whose format is defined below.
7548 otherwise it is @var{false-value}.
7554 expressions. The value of the @code{cond} expression is that of the
7555 @var{value} corresponding to the first true @var{test} expression. If
7557 expression is that of the @var{default} expression.
7565 This test is true if @var{i} is nonzero and false otherwise.
7571 @itemx (ior @var{test1} @var{test2})
7572 @itemx (and @var{test1} @var{test2})
7573 These tests are true if the indicated logical function is true.
7582 string).
7584 The @var{constraints} operand is ignored and should be the null string.
7588 The test is true if C expression @var{c-expr} is true. In non-constant
7593 The rtl instruction under test.
7595 The @code{define_insn} alternative that @var{insn} matches.
7596 @xref{Output Statement}.
7598 An array of @var{insn}'s rtl operands.
7603 0 or 1 value. For example, the following two tests are equivalent:
7640 expressions is true. Arithmetic expressions are formed with
7643 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
7647 Lengths},for additional forms). @code{symbol_ref} is a string
7649 @samp{get_attr_@dots{}} routine. It should normally be a global
7650 variable.
7654 @var{name} is a string specifying the name of an attribute.
7658 value or list. If @var{value} does not begin with a @samp{!}, this
7660 insn is in the list specified by @var{value}. If @var{value} begins
7662 @emph{not} in the specified list.
7679 (@pxref{Output Statement}) and the values must be small integers. For
7696 a particular pattern. This is by far the most common case.
7702 scheduled.
7704 @var{name} is a string specifying one of a fixed set of flags to test.
7706 direction of a conditional branch. Test the flags @code{very_likely},
7708 if a conditional branch is expected to be taken.
7711 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
7715 for backward branches which are not taken (annul-false).
7727 @code{insn} being scheduled is not a conditional branch.
7730 @code{insn} being scheduled is not a conditional branch.
7732 @code{insn} being scheduled is not a conditional branch.
7735 meaning to other passes of the compiler.
7739 The value of another attribute is returned. This is most useful
7741 produce more efficient code for non-numeric attributes.
7753 generated it). Every @code{define_insn} and @code{define_peephole} can
7755 matching insns. The value of any attribute not specified in a particular
7757 @code{define_attr}. Extensive use of default values for attributes
7760 next section.
7764 the value for a single attribute. The most general way of assigning an
7766 @code{attr} expression giving the name of the attribute being set. The
7768 (@pxref{Expressions}) giving the value of the attribute.
7771 (i.e., which is the applicable alternative in the constraint of the
7772 insn), the @code{set_attr_alternative} expression can be used. It
7774 each alternative.
7780 of attribute values, one for each alternative.
7782 The form of each of the above specifications is shown below. In each case,
7783 @var{name} is a string specifying the attribute to be set.
7789 succeeding alternatives. The number of elements must match the number
7790 of alternatives in the constraint of the insn pattern.
7794 that alternative.
7799 specified values. This is a shorthand for using a @code{cond} with
7800 tests on the @samp{alternative} attribute.
7806 attribute being set. @var{value} is the value of the attribute.
7829 statement. It has the form:
7837 @code{define_insn} and the @code{define_peephole} expressions.
7839 These values will typically be the ``worst case'' attribute values. For
7840 example, they might indicate that the condition code will be clobbered.
7842 A specification for a @code{length} attribute is handled specially. The
7847 string. Therefore, the value of the @code{length} attribute specified
7849 of a single machine instruction.
7859 insn attributes. Typically, insns are divided into @dfn{types} and an
7861 value. This attribute is normally used only to define the default value
7862 for other attributes. An example will clarify this usage.
7865 full-word operations are performed in registers. Let us assume that we
7867 operations, floating point operations, and branches.
7874 modified.
7906 full-word result.
7916 for different length branch displacements. In most cases, the assembler
7917 will choose the correct instruction to use. However, when the assembler
7919 attribute, is defined. This attribute must be defined to have numeric
7920 values by specifying a null string in its @code{define_attr}.
7929 must be a @code{label_ref}.
7933 This refers to the address of the @emph{current} insn. It might have
7936 current insn is to be computed.
7942 @code{length} attribute. In the case of @code{addr_vec} and
7944 the number of vectors multiplied by the size of each vector.
7946 Lengths are measured in addressable storage units (bytes).
7954 function of the context in which it is used. @var{length} is an lvalue
7956 updated with the correct length of the insn.
7958 This macro will normally not be required. A case in which it is
7959 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7961 may be required.
7968 example below illustrates.
7971 the IBM 360. If we adopt the convention that a register will be set to
7973 the start using a four-byte instruction. Otherwise, we need a six-byte
7974 sequence to load the address from memory and then branch to it.
8002 is constant for a given run of the compiler. Constant attributes may be
8003 used to specify which variety of processor is used. For example,
8020 does not depend on any particular insn. RTL expressions used to define
8023 forms involving insn attributes.
8032 delay slots, if any, on a target machine. An instruction is said to
8034 after the instruction are executed as if they were located before it.
8036 the following instruction before the branch or call is performed.
8039 @dfn{annul} instructions in the delay slot. This means that the
8040 instruction will not be executed for certain branch outcomes. Both
8042 annul if the branch is false are supported.
8047 instructions. See the next section for a discussion of data-dependent
8048 instruction scheduling.
8052 via the @code{define_delay} expression. It has the following form:
8062 @code{define_delay} applies to a particular insn. If so, the number of
8064 as the second argument. An insn placed in delay slot @var{n} must
8065 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8067 is true. Similarly, @var{annul-false-n} specifies which insns in the
8068 delay slot may be annulled if the branch is false. If annulling is not
8069 supported for that delay slot, @code{(nil)} should be coded.
8080 Multiple @code{define_delay} expressions may be specified. In this
8083 expressions are both true.
8100 @c the above is *still* too long. --mew 4feb93
8123 instructions can be executed simultaneously. An instruction starts
8124 execution if its issue conditions are satisfied. If not, the
8125 instruction is stalled until its conditions are satisfied. Such
8127 of successor instructions (or demands nop instructions, e.g.@: for some
8128 MIPS processors).
8130 There are two major kinds of interlock delays in modern processors.
8132 latency time}. The instruction execution is not started until all
8136 instruction execution start). Taking the data dependence delays into
8137 account is simple. The data dependence (true, output, and
8139 constant. In most cases this approach is adequate. The second kind
8140 of interlock delays is a reservation delay. The reservation delay
8142 processors resources, i.e.@: buses, internal registers, and/or
8143 functional units, which are reserved for some time. Taking this kind
8145 processors.
8148 instruction scheduler. For a better solution to this problem, the
8150 processor parallelism (or @dfn{pipeline description}). GCC
8153 @dfn{regular expressions}.
8157 on a given simulated processor cycle. The pipeline hazard recognizer is
8158 automatically generated from the processor pipeline description. The
8162 automaton state to another one. This algorithm is very fast, and
8165 processor complexity. To limit this effect, machine descriptions
8168 this does cause a small decrease in the algorithm's performance.}.
8172 an automaton-based processor pipeline description. The order of
8174 important.
8179 generated and used for the pipeline hazards recognition. Sometimes
8181 recognizer is large. If we use more than one automaton and bind functional
8183 less than the size of the single automaton. If there is no one such
8184 construction, only one finite state automaton is generated.
8190 @var{automata-names} is a string giving names of the automata. The
8191 names are separated by commas. All the automata should have unique names.
8193 @code{define_query_cpu_unit}.
8198 reservations should be described by the following construction.
8205 separated by commas. Don't use name @samp{nothing}, it is reserved
8206 for other goals.
8209 which the unit is bound. The automaton should be described in
8210 construction @code{define_automaton}. You should give
8211 @dfn{automaton-name}, if there is a defined automaton.
8214 units in insn reservations. The most important constraint is: if a
8218 reservation. The rest of the constraints are mentioned in the
8219 description of the subsequent constructions.
8224 to @code{define_cpu_unit}. The reservation of such units can be
8225 queried for an automaton state. The instruction scheduler never
8226 queries reservation of functional units for given automaton state. So
8227 as a rule, you don't need this construction. This construction could
8228 be used for future code generation goals (e.g.@: to generate
8229 @acronym{VLIW} insn templates).
8236 separated by commas.
8239 which the unit is bound.
8246 characteristics of an instruction.
8254 instruction. There is an important difference between the old
8255 description and the automaton based pipeline description. The latency
8256 time is used for all dependencies when we use the old description. In
8258 used for true dependencies. The cost of anti-dependencies is always
8261 is negative, the cost is considered to be zero). You can always
8263 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8265 @var{insn-name} is a string giving the internal name of the insn. The
8267 the automaton description file generated for debugging. The internal
8268 name has nothing in common with the names in @code{define_insn}. It is a
8269 good practice to use insn classes described in the processor manual.
8272 construction. You should remember that you will be in trouble if
8274 @code{define_insn_reservation} constructions is TRUE for an insn. In
8275 this case what reservation will be used for the insn is not defined.
8279 contain @code{symbol_ref}). It is also not checked during the
8281 recognizer considerably.
8284 units by the instruction. The reservations are described by a regular
8310 the reservation.
8315 regular expression @strong{or} etc.
8320 second regular expression @strong{and} etc.
8325 advancing (see @samp{,}).
8329 functional unit.
8333 @samp{define_reservation}.
8336 @samp{nothing} denotes no unit reservations.
8340 Sometimes unit reservations for different insns contain common parts.
8348 @var{reservation-name} is a string giving name of @var{regexp}.
8350 space. So the reservation names should be different from the
8351 functional unit names and can not be the reserved name @samp{nothing}.
8357 latency time for given instruction pair. This is so called bypasses.
8366 instructions given in string @var{in_insn_names}. Each of these
8368 they refer to the names of @code{define_insn_reservation}s.
8375 @samp{cpu1_load_}.
8378 defines an additional guard for the bypass. The function will get the
8379 two insns as parameters. If the function returns zero the bypass will
8380 be ignored for this case. The additional guard is necessary to
8381 recognize complicated bypasses, e.g.@: when the consumer is only an address
8382 of insn @samp{store} (not a stored value).
8386 guard function returns nonzero. If there is no such bypass, then
8387 bypass without the guard function is chosen.
8398 of small instructions into @acronym{VLIW} instruction slots. They
8399 can be used for @acronym{RISC} processors, too.
8410 separated by commas.
8413 separated by comma. Currently pattern is one unit or units
8414 separated by white-spaces.
8418 with a unit whose name is in the second string and vice versa. For
8420 (e.g.@: some SPARC processors) with a fully pipelined floating point
8422 point insns or only double floating point insns.
8427 reserved. This is an asymmetric relation. For example, it is useful
8429 @samp{slot0} reservation. We could describe it by the following
8437 reservation. In this case we could write
8444 @samp{presence_set}. The difference between them is when checking is
8445 done. When an instruction is issued in given automaton state
8447 state is changed. The first state is a source state, the second one
8448 is a result state. Checking for @samp{presence_set} is done on the
8450 done on the result reservation. This construction is useful to
8451 describe a reservation which is actually two subsequent reservations.
8459 @samp{slot0} which is absent in the source state).
8465 but it can be issued if we use analogous @samp{final_presence_set}.
8469 whose names are in the second string is not reserved. This is an
8471 this one but it is symmetric). For example it might be useful in a
8473 after either @samp{slot1} or @samp{slot2} have been reserved. This
8481 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8489 automaton.
8493 reservation. See comments for @samp{final_presence_set}.
8500 the following construction.
8507 code. Currently there are the following options:
8511 @dfn{no-minimization} makes no minimization of the automaton. This is
8513 look more accurately at reservations of states.
8517 automata.
8521 such as the number of DFA states, NDFA states and arcs.
8524 @dfn{v} means a generation of the file describing the result automata.
8525 The file has suffix @samp{.dfa} and can be used for the description
8526 verification and debugging.
8530 non-critical errors.
8534 two data structures and comparing them for space efficiency. Using
8536 very expensive to construct. This option is useful if the build
8537 process spends an unacceptably long time in genautomata.
8540 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8541 the treatment of operator @samp{|} in the regular expressions. The
8543 if the reservation is not possible, the second alternative. The
8545 may be rejected by reservations in the subsequent insns.
8549 producing an automaton. An additional state transition to collapse a
8551 state is generated. It can be triggered by passing @code{const0_rtx} to
8552 state_transition. In such an automaton, cycle advance transitions are
8553 available only for these collapsed states. This option is useful for
8555 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
8559 were generated so far for automaton being processed. This is useful
8560 during debugging a @acronym{DFA} description. If you see too many
8563 huge automaton.
8568 the cycle but can finish only two insns. To describe this, we define
8569 the following functional units.
8577 their result is ready in two cycles. The simple integer insns are
8579 are issued into the second pipeline. Integer division and
8582 cycles. The integer division is not pipelined, i.e.@: the subsequent
8584 insn finished. Floating point insns are fully pipelined and their
8585 results are ready in 3 cycles. Where the result of a floating point
8587 incurred. To describe all of this we could specify
8630 execution, or predication. The hallmark of this feature is the
8631 ability to nullify most of the instructions in the instruction set.
8634 @file{.md} file. An alternative is the @code{define_cond_exec} template.
8645 insn to be executed at runtime and should match a relational operator.
8647 at once. Any @code{match_operand} operands must have no more than one
8648 alternative.
8651 pattern to match.
8656 and @samp{@@} special cases do not apply. This is only useful if the
8657 assembly text for the predicate is a simple prefix to the main insn.
8660 if the current insn is predicated, and will otherwise be @code{NULL}.
8663 the @code{predicable} instruction attribute is made.
8664 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
8666 values being @code{no} and @code{yes}. The default and all uses in
8667 the insns must be a simple constant, not a complex expressions. It
8669 list of values. If that is the case, the port should also define an
8671 should also allow only @code{no} and @code{yes} as its values.
8675 generated that matches a predicated version of the instruction.
8689 "@var{test2}"
8703 "(@var{test2}) && (@var{test1})"
8715 can be a maintenance problem.
8718 expression. It contains a vector of name-value pairs. From that
8720 if the corresponding value had been written instead. You may use
8722 constants to the table. It is an error to redefine a constant with
8723 a different value.
8759 in the insn-codes.h header file as #defines.
8763 You can also use the machine description file to define enumerations.
8765 are visible to both the machine description file and the main C code.
8779 in @file{insn-constants.h}:
8791 where @var{cname} is the capitalized form of @var{name}.
8800 begins with @var{cname}.
8803 you like. The above example is directly equivalent to:
8813 individual @code{.md} file. For example, if a port defines its
8814 synchronization instructions in a separate @file{sync.md} file,
8816 values in @file{sync.md} rather than in the main @file{.md} file.
8824 when printing out @code{unspec_volatile} expressions. For example:
8835 (unspec_volatile ... UNSPECV_BLOCKAGE)
8841 it when printing out @code{unspec} expressions. GCC will also use
8843 @code{unspecv} enumeration is also defined. You can therefore
8846 for both.
8874 where @var{cvaluei} is the capitalized form of @var{valuei}.
8877 (@pxref{define_enum_attr}).
8882 @cindex iterators in @file{.md} files
8885 mode or for more than one rtx code. GCC provides some simple iterator
8886 facilities to make this process easier.
8889 * Mode Iterators:: Generating variations of patterns for different modes.
8890 * Code Iterators:: Doing the same for codes.
8895 @cindex mode iterators in @file{.md} files
8897 Ports often need to define similar patterns for two or more different modes.
8904 very similar to the @code{DFmode} ones.
8909 @code{SImode} and @code{DImode} patterns for manipulating pointers.
8913 @file{.md} file template. They can be used with any type of
8915 @code{define_split}, or @code{define_peephole2}.
8918 * Defining Mode Iterators:: Defining a new mode iterator.
8933 This allows subsequent @file{.md} file constructs to use the mode suffix
8934 @code{:@var{name}}. Every construct that does so will be expanded
8937 and so on. In the expansion for a particular @var{modei}, every
8938 C condition will also require that @var{condi} be true.
8946 defines a new mode suffix @code{:P}. Every construct that uses
8948 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
8950 the @code{:DI} version will only apply if @code{Pmode == DImode}.
8952 As with other @file{.md} conditions, an empty string is treated
8953 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
8954 to @code{@var{mode}}. For example:
8961 but that the @code{:SI} expansion has no such constraint.
8963 Iterators are applied in the order they are defined. This can be
8965 substitutions. @xref{Substitutions}.
8971 If an @file{.md} file construct uses mode iterators, each version of the
8972 construct will often need slightly different strings or modes. For
8979 appropriate mode name for @var{m}.
8983 each instruction will often use a different assembler mnemonic.
8988 mode for the other operand(s).
8991 GCC supports such variations through a system of ``mode attributes''.
8994 upper case. You can define other attributes using:
9001 is the value associated with @var{modei}.
9006 mode attribute. If the attribute is defined for @var{mode}, the whole
9008 value.
9010 For example, suppose an @file{.md} file has:
9020 @code{"ld\t%0,%1"}.
9032 substitution will be attempted for every iterator expansion.
9037 Here is an example from the MIPS port. It defines the following
9083 @cindex code iterators in @file{.md} files
9087 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9096 @var{codei} if condition @var{condi} is true. Each @var{codei}
9097 must have the same rtx format. @xref{RTL Classes}.
9101 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9102 @xref{Defining Mode Iterators}.
9104 It is possible to define attributes for codes as well as for modes.
9106 code in lower case, and @code{CODE}, the name of the code in upper case.