[llvm][AArch64][Assembly]: Add SME_F8F16 and SME_F8F32 Ass/Disass. (#70640)

This patch adds the feature flags of SME_F8F16 and SME_F8F32,
and the assembly/disassembly for the following instruction

[llvm][AArch64][Assembly]: Add SME_F8F16 and SME_F8F32 Ass/Disass. (#70640)

This patch adds the feature flags of SME_F8F16 and SME_F8F32,
and the assembly/disassembly for the following instructions of SME2:

* SME:
- FMLAL, FMLALL
- FVDOT, FVDOTT
- FVDOTB
- FMOPA

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

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[llvm][AArch64][Assembly]: Add LUT assembly/disassembly. (#70802)

This patch adds the feature flags of LUT and SME_LUTv2, and the
assembly/disassembly
for the following instructions of NEON, SVE2

[llvm][AArch64][Assembly]: Add LUT assembly/disassembly. (#70802)

This patch adds the feature flags of LUT and SME_LUTv2, and the
assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON:
- LUT2
- LUT4
* SVE2:
- LUTI2_ZZZI
- LUTI4_ZZZI
- LUTI4_Z2ZZI
* SME:
- MOVT
- LUTI4_4ZZT2Z
- LUTI4_S_4ZZT2Z

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

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[llvm][AArch64][Assembly]: Add FDOT2/FDOT4 assembly and disassembly. (#70237)

This patch adds the feature flag FDOT2/FDOT4 and the
assembly/disassembly
for the following instructions of NEON and

[llvm][AArch64][Assembly]: Add FDOT2/FDOT4 assembly and disassembly. (#70237)

This patch adds the feature flag FDOT2/FDOT4 and the
assembly/disassembly
for the following instructions of NEON and SVE2:
* NEON:
- FDOTlane
- FDOT
* SVE2:
- FDOT_ZZZI_BtoH
- FDOT_ZZZ_BtoH
- FDOT_ZZZI_BtoS
- FDOT_ZZZ_BtoS

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

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[llvm][AArch64][Assembly]: Add FP8FMA assembly and disassembly. (#70134)

This patch adds the feature flag FP8FMA and the assembly/disassembly
for the following instructions of NEON and SVE2:
*

[llvm][AArch64][Assembly]: Add FP8FMA assembly and disassembly. (#70134)

This patch adds the feature flag FP8FMA and the assembly/disassembly
for the following instructions of NEON and SVE2:
* NEON:
- FMLALBlane
- FMLALTlane
- FMLALLBBlane
- FMLALLBTlane
- FMLALLTBlane
- FMLALLTTlane
- FMLALB
- FMLALT
- FMLALLB
- FMLALLBT
- FMLALLTB
- FMLALLTT
* SVE2:
- FMLALB_ZZZI
- FMLALT_ZZZI
- FMLALB_ZZZ
- FMLALT_ZZZ
- FMLALLBB_ZZZI
- FMLALLBT_ZZZI
- FMLALLTB_ZZZI
- FMLALLTT_ZZZI
- FMLALLBB_ZZZ
- FMLALLBT_ZZZ
- FMLALLTB_ZZZ
- FMLALLTT_ZZZ

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

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[LLVM][AArch64][Assembly]: Add FAMINMAX assembly/disasse… (#70115)

…mbly.

This patch adds the feature flag FAMINMAX and the assembly/disassembly
for the following instructions of NEON, SVE2 and

[LLVM][AArch64][Assembly]: Add FAMINMAX assembly/disasse… (#70115)

…mbly.

This patch adds the feature flag FAMINMAX and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON:
- FAMIN
- FAMAX
* SVE2:
- FAMIN_ZPmZ
- FAMAX_ZPmZ
* SME2:
- FAMAX_2Z2Z
- FAMIN_2Z2Z
- FAMAX_4Z4Z
- FAMIN_4Z4Z

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

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[llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#69632)

This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and

[llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#69632)

This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON Instructions:
+ Advanced SIMD two-register miscellaneous:
- F1CVTL, F1CVTL2, F2CVTL, F2CVTL2
- BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
+ Advanced SIMD three-register extension:
- FCVTN, FCVTN2 (FP32 to FP8)
- FCVTN (FP16 to FP8)
+ Advanced SIMD three same:
- FSCALE
* SVE2 Instructions:
+ Downconvert instructions:
- FCVTN_Z2Z_HtoB
- FCVTNB_Z2Z_StoB
- BFCVTN_Z2Z_HtoB
- FCVTNT_Z2Z_StoB
+ Upconvert instructions:
- F1CVT_ZZ, F2CVT_ZZ
- BF1CVT_ZZ, BF2CVT_ZZ
- F1CVTLT_ZZ, F2CVTLT_ZZ
- BF1CVTLT_ZZ, BF2CVTLT_ZZ

* SME2 Instructions:
- F1CVT_2ZZ, F2CVT_2ZZ
- BF1CVT_2ZZ, BF2CVT_2ZZ
- F1CVTL_2ZZ, F2CVTL_2ZZ
- BF1CVTL_2ZZ, BF2CVTL_2ZZ
- FCVT_Z2Z_HtoB, BFCVT_Z2Z_HtoB
- FCVT_Z4Z - FCVTN_Z4Z
- FSCALE_2ZZ, FSCALE_4ZZ
- FSCALE_2Z2Z, FSCALE_4Z4Z

That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

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[llvm][AArch64][Assembly] Implement support to read/write FPMR (#69618)

Also add Read only registers:
ID_AA64FPFR0_EL1
ID_AA64ISAR3_EL1

This is based on this documentation:
https://deve

[llvm][AArch64][Assembly] Implement support to read/write FPMR (#69618)

Also add Read only registers:
ID_AA64FPFR0_EL1
ID_AA64ISAR3_EL1

This is based on this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09

Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>

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[clang] Enable descriptions for --print-supported-extensions (#66715)

Enables summary descriptions along with the names of the feature.
Descriptions here are simply looked up via the available llvm

[clang] Enable descriptions for --print-supported-extensions (#66715)

Enables summary descriptions along with the names of the feature.
Descriptions here are simply looked up via the available llvm tablegen
data.

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[clang][ARM] Enable --print-supported-extensions for ARM (#66083)

```
$ ./bin/clang --target=arm-linux-gnueabihf --print-supported-extensions
<...>
All available -march extensions for ARM

[clang][ARM] Enable --print-supported-extensions for ARM (#66083)

```
$ ./bin/clang --target=arm-linux-gnueabihf --print-supported-extensions
<...>
All available -march extensions for ARM

crc
crypto
sha2
aes
dotprod
<...>
```

This follows the format set by RISC-V and AArch64. As for AArch64, ARM
doesn't have versioned extensions like RISC-V does. So there is only 1
column, which contains the name.

Any extension without a "feature" is hidden as these cannot be used with
-march.

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Don't rely in llvm::Bitset CTAD. NFC.

This triggers a lot of -Wctad-maybe-unsupported

[AArch64]: Refactor target parser to use Bitset. (#65423)

Use Bitset instead of BitMasking for the Architecture Extensions,
as the number of extensions will exceed the bitmask bits eventually.

[clang][AArch64] Add --print-supported-extensions support (#65466)

This follows the RISC-V work done in
4b40ced4e5ba10b841516b3970e7699ba8ded572.

This uses AArch64's target parser instead. We ju

[clang][AArch64] Add --print-supported-extensions support (#65466)

This follows the RISC-V work done in
4b40ced4e5ba10b841516b3970e7699ba8ded572.

This uses AArch64's target parser instead. We just list the names,
without the "+" on them, which matches RISC-V's format.

```
$ ./bin/clang -target aarch64-linux-gnu --print-supported-extensions
clang version 18.0.0 (https://github.com/llvm/llvm-project.git 154da8aec20719c82235a6957aa6e461f5a5e030)
Target: aarch64-unknown-linux-gnu
Thread model: posix
InstalledDir: <...>
All available -march extensions for AArch64

aes
b16b16
bf16
brbe
crc
crypto
cssc
<...>
```

Since our extensions don't have versions in the same way there's just
one column with the name in.

Any extension without a feature name (including the special "none") is
not listed as those cannot be passed to -march, they're just for the
backend. For example the MTE extension can be added with "+memtag" but
MTE2 and MTE3 do not have feature names so they cannot be added to
-march.

This does not attempt to tackle the fact that clang allows invalid
combinations of AArch64 extensions, it simply lists the possible
options. It's still up to the user to ask for something sensible.

Equally, this has no context of what CPU is being selected. Neither does
the RISC-V option, the user has to be aware of that.

I've added a target parser test, and a high level clang test that checks
RISC-V and AArch64 work and that Intel, that doesn't support this, shows
the correct error.

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[ARM][NFC] Use FPUKind enum instead of unsigned

Also rename some FPUID variables to FPUKind now it's clear that's what
they are.

Differential Revision: https://reviews.llvm.org/D146141

[AArch64] Assembly Support for FEAT_GCS/FEAT_CHK

This implements support for two new 2022 A-profile extensions:
- FEAT_CHK - Check Feature Status Extension
- FEAT_GCS - Guarded Control Stacks

FEAT_

[AArch64] Assembly Support for FEAT_GCS/FEAT_CHK

This implements support for two new 2022 A-profile extensions:
- FEAT_CHK - Check Feature Status Extension
- FEAT_GCS - Guarded Control Stacks

FEAT_CHK is mandatory from armv8.0-a, but is in the hint space so
there's no clang command-line flag for it, and we only print the hint as
`chkfeat x16` at v8.9a and above, to be compatible when using a
non-integrated assembler that might not yet know about the extension.

FEAT_GCS is optional from armv9.4-a onwards. It is enabled using `+gcs`
in a clang `-march=` or `-mcpu=` option string, or using a
`.arch_extension gcs` assembly directive.

This patch includes changes by Ties Stuij, Tomas Matheson, and Keith
Walker.

Differential Revision: https://reviews.llvm.org/D145563

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[AArch64] Replace AEK_CRYPTO with relevant features in cpu definitions

This replaces AEK_CRYPTO in the AArch64TargetParser definitions,
replacing the composite Crypto features with the constituent p

[AArch64] Replace AEK_CRYPTO with relevant features in cpu definitions

This replaces AEK_CRYPTO in the AArch64TargetParser definitions,
replacing the composite Crypto features with the constituent parts.
AEK_CRYPTO is replaced with either AEK_AES | AEK_SHA2 or AEK_AES |
AEK_SHA2 | AEK_SHA3 | AEK_SHA4 depending on if the cpu is Arm-v8.4+.
This helps get the features correct in some more places like
target(cpu=..) attributes.

Otherwise this is hopefully an NFC for -mcpu options but seems like a
cleaner design.

Differential Revision: https://reviews.llvm.org/D142548

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[NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

This updates the AArch64's Target Parser and its uses to capture
information about default features directly from ArchI

[NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects

This updates the AArch64's Target Parser and its uses to capture
information about default features directly from ArchInfo and CpuInfo
objects, instead of relying on an API function to access them
indirectly.

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D142540

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[NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

This updates the parsing methods in AArch64's Target Parser to make use
of optional returns instead of "invalid" enu

[NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects

This updates the parsing methods in AArch64's Target Parser to make use
of optional returns instead of "invalid" enum values, making the API's
behaviour clearer.

Reviewed By: lenary, tmatheson

Differential Revision: https://reviews.llvm.org/D142539

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AArch64: remove SM4 support from Apple CPUs.

The CPUs never supported SM4 instructions, but until recently I think crypto
was folded into the baseline architecture as a monolithic feature so it was

AArch64: remove SM4 support from Apple CPUs.

The CPUs never supported SM4 instructions, but until recently I think crypto
was folded into the baseline architecture as a monolithic feature so it was
difficult to represent that. Now it's split we can, and the CPUs that support
v8.4 onwards only handle AES, SHA2, SHA3 by way of crypto instructions.

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[AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
* memory tagging is supported
* SM3/SM4 are supported
* adds a new fusion pair for (A+B+1 and

[AArch64] Add the Ampere1A core

The Ampere1A core improves on the Ampere1 with key differences being:
* memory tagging is supported
* SM3/SM4 are supported
* adds a new fusion pair for (A+B+1 and A-B-1)
(added in a later commit)

Depends on D142395

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D142396

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[AArch64] Update enabled extensions for Ampere1 core

The original enablement for the Ampere1 core inadvertently had omitted
that FEAT_RAND is support and errorously claimed that FEAT_MTE was
availab

[AArch64] Update enabled extensions for Ampere1 core

The original enablement for the Ampere1 core inadvertently had omitted
that FEAT_RAND is support and errorously claimed that FEAT_MTE was
available.

Adjust the definition of Ampere1 to match reality.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D142395

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[TargetParser] Remove an EXPECT that is never executed

Found by the Rotten Green Tests project.

[AAch64] Format TargetParserTest ARMCPUTestParams table. NFC

[AArch64] Remove AES, SHA2, SHA3 and SM4 features from armv8.6-a+

The Armv8.6-a and later architecture definitions included AES, SHA2,
SHA3 and SM4, but this did not have an effect when specifying
-

[AArch64] Remove AES, SHA2, SHA3 and SM4 features from armv8.6-a+

The Armv8.6-a and later architecture definitions included AES, SHA2,
SHA3 and SM4, but this did not have an effect when specifying
-march=armv8.6-a. The did not set preprocessor features
(https://godbolt.org/z/1YKad6M8e) or enable the relevant instructions
(like eor3 from sha3: https://godbolt.org/z/vY9v4MqvG). Similarly
architectures armv8 to armv8.5 defined +crypto, but this did not effect
the -march's, only the -mcpu with those architectures. I believe this
was working as intended.

After D141411 we now add the default features for architectures except
for +crypto, which has had the effect of enabling aes/sha2/sha3/sm4 when
-march=armv8.6-a is used. This patch removed those crypto features
again, going back to how things were before. It also removes the
AEK_CRYPTO feature from lower architecture levels, moving it to the cpus
that use it. This shouldn't make any changes, but a few extra tests have
been added for preprocessor features that have improved since llvm 15.

The -mcpu=ampere1 cpu is the only armv8.6+ cpu at present. For that, the
AES, SHA2 and SHA3 features have been re-added to the CPU definition to
keep it in-line with the gcc definition from
https://github.com/gcc-mirror/gcc/commit/db2f5d661239737157cf131de7d4df1c17d8d88d.

Differential Revision: https://reviews.llvm.org/D141606

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[AArch64] Add command line support for v9.4-A's Instrumentation Extension

This introduces command line support (`+ite`) for the v9.4-A's
Instrumentation Extension (FEAT_ITE).

Patch by Son Tuan Vu.

[AArch64] Add command line support for v9.4-A's Instrumentation Extension

This introduces command line support (`+ite`) for the v9.4-A's
Instrumentation Extension (FEAT_ITE).

Patch by Son Tuan Vu.

Reviewed By: lenary, tmatheson

Differential Revision: https://reviews.llvm.org/D141403

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[AArch64] Armv9-A implies FP16

As Armv9-a implies SVE2 it implies SVE (added in D141411) and so it
should also imply FP16, which this patch adds. This helps get the target
features correct when usin

[AArch64] Armv9-A implies FP16

As Armv9-a implies SVE2 it implies SVE (added in D141411) and so it
should also imply FP16, which this patch adds. This helps get the target
features correct when using `target("arch=armv9-a")` attributes.

There is also an adjustment to AssertSameExtensionFlags in this patch to
make it print cpu names, useful when the TargetParser unit tests are run
through lit to distinguish which cpu is failing.

Differential Revision: https://reviews.llvm.org/D142087

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