Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"

This reverts commit 89c1bf1230e011f2f0e43554c278205fa1819de5.

This has been unimplemenented for a while, and GCC does not implement
it, there

Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"

This reverts commit 89c1bf1230e011f2f0e43554c278205fa1819de5.

This has been unimplemenented for a while, and GCC does not implement
it, therefore we need to consider whether we should just deprecate it
in the ACLE instead.

show more ...

[ARM] __ARM_ARCH macro definition fix (#81493)

This patch changes how the macro __ARM_ARCH is defined to match its
defintion in the ACLE. In ACLE 5.4.1, __ARM_ARCH is defined as equal to
the major

[ARM] __ARM_ARCH macro definition fix (#81493)

This patch changes how the macro __ARM_ARCH is defined to match its
defintion in the ACLE. In ACLE 5.4.1, __ARM_ARCH is defined as equal to
the major architecture version for ISAs up to and including v8. From
v8.1 onwards, its definition is changed to include minor versions, such
that for an architecture vX.Y, __ARM_ARCH = X*100 + Y. Before this
patch, LLVM defined __ARM_ARCH using only the major architecture version
for all architecture versions. This patch adds functionality to define
__ARM_ARCH correctly for architectures greater than or equal to v8.1.

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[AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-chan

[AArch64] Add the Ampere1B core (#81297)

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.

Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.

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[llvm][unittests] Put human-readable names on TargetParserTests. NFC (#80749)

Before:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUT

[llvm][unittests] Put human-readable names on TargetParserTests. NFC (#80749)

Before:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/8
...
```

After:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
...
```

Which improves the experience of finding and running this:
```
$ ./unittests/TargetParser/TargetParserTests --gtest_filter=AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
Note: Google Test filter = AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture (0 ms total)

[----------] Global test environment tear-down
[==========] 1 test from 1 test suite ran. (0 ms total)
[ PASSED ] 1 test.
```

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[AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)

Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.

After adding AEK_PAUTH, s

[AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)

Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.

After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.

The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.

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[AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (#79614)

With a690e86 we added -mcpu/mtune=native support to handle the Microsoft
Azure Cobalt 100 CPU as a Neoverse N2. This

[AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (#79614)

With a690e86 we added -mcpu/mtune=native support to handle the Microsoft
Azure Cobalt 100 CPU as a Neoverse N2. This patch adds a CPU alias in
TargetParser to maintain compatibility with GCC.

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[ARM] Introduce the v9.5-A architecture version to Arm targets (#78994)

This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArc

[ARM] Introduce the v9.5-A architecture version to Arm targets (#78994)

This introduces the Armv9.5-A architecture version to the Arm backend,
following on from the existing implementation for AArch64 targets.

Mode details about the Armv9.5-A architecture version can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

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[AArch64][Driver] Better handling of target feature dependencies (#78270)

Currently there are several bits of code in the AArch64 driver which
attempt to enforce dependencies between optional featu

[AArch64][Driver] Better handling of target feature dependencies (#78270)

Currently there are several bits of code in the AArch64 driver which
attempt to enforce dependencies between optional features in the -march=
and -mcpu= options. However, these are based on the list of feature
names being enabled/disabled, so they have a lot of logic to consider
the order in which features were turned on and off, which doesn't scale
well as dependency chains get longer.

This patch moves the code handling these dependencies to TargetParser,
and changes them to use a Bitset of enabled features. This makes it easy
to check which features are enabled, and is converted back to a list of
LLVM feature names once all of the command-line options are parsed.

The motivating example for this was the -mcpu=cortex-r82+nofp option.
Previously, the code handling the dependency between the fp16 and
fp16fml extensions did not consider the nofp modifier, so it added
+fullfp16 to the feature list. This should have been disabled by the
+nofp modifier, and also the backend did follow the dependency between
fullfp16 and fp, resulting in fp being turned back on in the backend.

Most of the dependencies added to AArch64TargetParser.h weren't known
about by clang before, I built that list by checking what the backend
thinks the dependencies between SubtargetFeatures are.

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[TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (#75516)

This patch defines AEK_JSCVT and AEK_FCMA for CPU features FEAT_JSCVT
and FEAT_FCMA respectively, and add them to the feature set of

[TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (#75516)

This patch defines AEK_JSCVT and AEK_FCMA for CPU features FEAT_JSCVT
and FEAT_FCMA respectively, and add them to the feature set of TSV110.

show more ...

[AArch64] Correct features for Arm Cortex-A78C, Cortex-X1C and Cortex-X2 (#76932)

Remove AArch64::AEK_FP16ML from Arm Cortex-A78C definition, as
this is not supported, according to the Technical Re

[AArch64] Correct features for Arm Cortex-A78C, Cortex-X1C and Cortex-X2 (#76932)

Remove AArch64::AEK_FP16ML from Arm Cortex-A78C definition, as
this is not supported, according to the Technical Reference Manual:
https://developer.arm.com/documentation/102226/latest/

Also add AArch64::AEK_FLAGM (Flag Manipulation) to Arm Cortex-X1C
and Arm Cortex-X2 as these were missing previously, but are
supported, according to the Technical Reference Manuals:
https://developer.arm.com/documentation/101968/latest/
https://developer.arm.com/documentation/101803/latest/

Fixes #62383

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[AArch64] Assembly support for the Armv9.5-A Memory System Extensions (#76237)

This implements assembly support for the Memory Systems Extensions
introduced as part of the Armv9.5-A architecture ve

[AArch64] Assembly support for the Armv9.5-A Memory System Extensions (#76237)

This implements assembly support for the Memory Systems Extensions
introduced as part of the Armv9.5-A architecture version.
The changes include:
* New subtarget feature for FEAT_TLBIW.
* New system registers for FEAT_HDBSS:
* HDBSSBR_EL2 and HDBSSPROD_EL2.
* New system registers for FEAT_HACDBS:
* HACDBSBR_EL2 and HACDBSCONS_EL2.
* New TLBI instructions for FEAT_TLBIW:
* VMALLWS2E1(nXS), VMALLWS2E1IS(nXS) and VMALLWS2E1OS(nXS).
* New system register for FEAT_FGWTE3:
* FGWTE3_EL3.

show more ...

Re-land "[AArch64] Codegen support for FEAT_PAuthLR" (#75947)

This reverts commit 9f0f5587426a4ff24b240018cf8bf3acc3c566ae.

Fix expensive checks failure by properly marking register def for ADR.

Revert "[AArch64] Codegen support for FEAT_PAuthLR"

This reverts commit 5992ce90b8c0fac06436c3c86621fbf6d5398ee5.

Builtbot failures with expensive checks enabled.

[AArch64] Codegen support for FEAT_PAuthLR

- Adds a new +pc option to -mbranch-protection that will enable
the use of PC as a diversifier in PAC branch protection code.

- When +pauth-lr is enable

[AArch64] Codegen support for FEAT_PAuthLR

- Adds a new +pc option to -mbranch-protection that will enable
the use of PC as a diversifier in PAC branch protection code.

- When +pauth-lr is enabled (-march=armv9.5a+pauth-lr) in combination
with -mbranch-protection=pac-ret+pc, the new 9.5-a instructions
(pacibsppc, retaasppc, etc) are used.

Documentation for the relevant instructions can be found here:
https://developer.arm.com/documentation/ddi0602/2023-09/Base-Instructions/

Co-authored-by: Lucas Prates <lucas.prates@arm.com>

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Reland: [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)

This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of

Reland: [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)

This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.

The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register

Mode details about the extension can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>

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[llvm] Use StringRef::{starts,ends}_with (NFC)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,end

[llvm] Use StringRef::{starts,ends}_with (NFC)

This patch replaces uses of StringRef::{starts,ends}with with
StringRef::{starts,ends}_with for consistency with
std::{string,string_view}::{starts,ends}_with in C++20.

I'm planning to deprecate and eventually remove
StringRef::{starts,ends}with.

show more ...

[AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (#75055)

Neoverse N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not

[AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (#75055)

Neoverse N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so -mcpu=neoverse-n2+crypto is required
to enable crypto for this core.

Neoverse N2 Technical Reference Manual:
https://developer.arm.com/documentation/102099/0003/

show more ...

[ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (#74822)

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
https://developer.arm.com/processors/cortex-m52

Revert HWASAN failure (#74163)

This is the failure:
https://lab.llvm.org/buildbot/#/builders/236/builds/7728/steps/10/logs/stdio

This started with eef8e1d206dc01c081a0ca29b7f9e0c39d33446e, but b

Revert HWASAN failure (#74163)

This is the failure:
https://lab.llvm.org/buildbot/#/builders/236/builds/7728/steps/10/logs/stdio

This started with eef8e1d206dc01c081a0ca29b7f9e0c39d33446e, but because
there were a couple of patches that came after that I had to revert all
3 of them because of merge conflicts.

show more ...

[AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)

This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Ar

[AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)

This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.

The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register

Mode details about the extension can be found at:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Co-authored-by: Rodolfo Wottrich <rodolfo.wottrich@arm.com>

show more ...

AArch64: add support for currently released Apple CPUs. (#73499)

These are still v8.6a and have no real changes as far as LLVM cares, so
it's mostly just a copy/paste job.

AArch64: switch Apple CPUs (that support it) to v8.6a. (#73497)

We pretended they were v8.5a in the past because LLVM's modelling used
to fold SM4 crypto support into v8.6a (which the CPUs don't ac

AArch64: switch Apple CPUs (that support it) to v8.6a. (#73497)

We pretended they were v8.5a in the past because LLVM's modelling used
to fold SM4 crypto support into v8.6a (which the CPUs don't actually
have). That's changed in the last year so we can use the real value.

This is mostly a tidy-up commit before one that'll bring in A17 and M3.

show more ...

[AArch64][SME] Add support for sme-fa64 (#70809)

[AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (#72395)

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
htt

[AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (#72395)

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani <sivan.shani@arm.com>

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[AArch64] Introduce the Armv9.5-A architecture version (#72392)

This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.

Mode details about the

[AArch64] Introduce the Armv9.5-A architecture version (#72392)

This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.

Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Patch by Oliver Stannard.

show more ...