[AArch64] remove pointless AEK_NONE (#97569)

[llvm][AArch64] Drop unused&redundant field in the TargetParserTest. NFC (#97367)

There were a couple of cases where this field was just plain wrong
because we weren't actually testing against it.

[llvm][AArch64] Drop unused&redundant field in the TargetParserTest. NFC (#97367)

There were a couple of cases where this field was just plain wrong
because we weren't actually testing against it. Instead, drop the
`CPUAttr` field on AArch64 tests.

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Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (#96795)

This introduces the new `--print-enabled-extensions` command line option
to AArch64, which prints the list

Re-land: "[AArch64] Add ability to list extensions enabled for a target" (#95805) (#96795)

This introduces the new `--print-enabled-extensions` command line option
to AArch64, which prints the list of extensions that are enabled for the
target specified by the combination of `--target`/`-march`/`-mcpu`
values.

The goal of the this option is both to enable the manual inspection of
the enabled extensions by users and to enhance the testability of
architecture versions and CPU targets implemented in the compiler.

As part of this change, a new field for `FEAT_*` architecture feature
names was added to the TableGen entries. The output of the existing
`--print-supported-extensions` option was updated accordingly to show
these in a separate column.

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Revert "[AArch64] Add ability to list extensions enabled for a target" (#96768)

Reverts llvm/llvm-project#95805 due to test failures caught by the
buildbots.

[AArch64] Add ability to list extensions enabled for a target (#95805)

This introduces the new `--print-enabled-extensions` command line option
to AArch64, which prints the list of extensions that

[AArch64] Add ability to list extensions enabled for a target (#95805)

This introduces the new `--print-enabled-extensions` command line option
to AArch64, which prints the list of extensions that are enabled for the
target specified by the combination of `--target`/`-march`/`-mcpu`
values.

The goal of the this option is both to enable the manual inspection of
the enabled extensions by users and to enhance the testability of
architecture versions and CPU targets implemented in the compiler.

As part of this change, a new field for `FEAT_*` architecture feature
names was added to the TableGen entries. The output of the existing
`--print-supported-extensions` option was updated accordingly to show
these in a separate column.

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[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a (#96007)

... so move it out of the `implied_features` list, and into the
`DefaultExts` list.

[AArch64][TargetParser] Split FMV and extensions (#92882)

FMV extensions are really just mappings from FMV feature names to lists
of backend features for codegen. Split them out into their own sepa

[AArch64][TargetParser] Split FMV and extensions (#92882)

FMV extensions are really just mappings from FMV feature names to lists
of backend features for codegen. Split them out into their own separate
file.

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[AArch64][TargetParser] move CPUInfo into tablegen [NFC] (#92145)

This is a follow up to #92037, which moved the architecture information.

Generate the AArch64TargetParser CPUInfo from tablegen P

[AArch64][TargetParser] move CPUInfo into tablegen [NFC] (#92145)

This is a follow up to #92037, which moved the architecture information.

Generate the AArch64TargetParser CPUInfo from tablegen Processor defs using a
new tablegen emitter. Some basic error checking is added in the emitter to
ensure that duplicate features are not added to the Processor defs.

The generic CPU becomes an entry in tablegen.

Some CPU features which were present in the CPUInfo but absent from the tablegen
defs have been added to tablegen. FeatureCrypto is replaced with FeatureSHA2 and
FeatureAES. This changes a few of the tests.

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[llvm][AArch64] Rearrange Apple CPUs by generation, not product class. NFC (#95579)

[llvm][AArch64] Support -mcpu=apple-m4 (#95478)

[AArch64] Add support for Cortex-A725 and Cortex-X925 (#95214)

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
https://developer.arm.com/docu

[AArch64] Add support for Cortex-A725 and Cortex-X925 (#95214)

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
https://developer.arm.com/documentation/102807/latest

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[AArch64] set A14/M1 architecture version to v8.4-a (#92600)

According to the Apple Silicon Optimization Guide, these are 8.4 with
all features of 8.5 except BTI.

[ARM] Add support for Cortex-R52+ (#94633)

Cortex-R52+ is an Armv8-R AArch32 CPU.

Technical Reference Manual for Cortex-R52+:
https://developer.arm.com/documentation/102199/latest/

[AArch64] Add support for Qualcomm Oryon processor (#91022)

Oryon is an ARM V8 AArch64 CPU from Qualcomm.

---------

Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>

[AArch64] Fix feature flags dependecies (#90612)

This patch removes FEAT_FPMR from list of available of architecture
features, instead enabling FMPR register by default.
Additionally dependencies

[AArch64] Fix feature flags dependecies (#90612)

This patch removes FEAT_FPMR from list of available of architecture
features, instead enabling FMPR register by default.
Additionally dependencies between architectural features are added and
fixed.

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[AArch64] move extension information into tablgen (#90987)

Generate TargetParser extension information from tablegen. This includes FMV extension information. FMV only extensions are represented by

[AArch64] move extension information into tablgen (#90987)

Generate TargetParser extension information from tablegen. This includes FMV extension information. FMV only extensions are represented by a separate tablegen class.

Use MArchName/ArchKindEnumSpelling to avoid renamings.
Cases where there is simply a case difference are handled by
consistently uppercasing the AEK_ name in the emitted code.

Remove some Extensions which were not needed.
These had AEK entries but were never actually used for anything.
They are not present in Extensions[] data.

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[llvm] Use StringRef::operator== instead of StringRef::equals (NFC) (#91441)

I'm planning to remove StringRef::equals in favor of
StringRef::operator==.

- StringRef::operator==/!= outnumber Stri

[llvm] Use StringRef::operator== instead of StringRef::equals (NFC) (#91441)

I'm planning to remove StringRef::equals in favor of
StringRef::operator==.

- StringRef::operator==/!= outnumber StringRef::equals by a factor of
70 under llvm/ in terms of their usage.

- The elimination of StringRef::equals brings StringRef closer to
std::string_view, which has operator== but not equals.

- S == "foo" is more readable than S.equals("foo"), especially for
!Long.Expression.equals("str") vs Long.Expression != "str".

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[ARM] Armv8-R does not require fp64 or neon. (#88287)

This was [addressed for AArch64
here](https://github.com/llvm/llvm-project/pull/79004), but the same
applies to ARM.

Move the enablement of

[ARM] Armv8-R does not require fp64 or neon. (#88287)

This was [addressed for AArch64
here](https://github.com/llvm/llvm-project/pull/79004), but the same
applies to ARM.

Move the enablement of neon+fp64 to `-mcpu=cortex-r52`, which optionally
supports these features.

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[AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (#90440)

[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:

[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
https://developer.arm.com/documentation/101595/latest/

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[AArch64] Remove Automatic Enablement of FEAT_F32MM (#85203)

When `+sve` is passed in the command line, if the Architecture being
targeted is V8.6A/V9.1A or later, `+f32mm` is also added. This enab

[AArch64] Remove Automatic Enablement of FEAT_F32MM (#85203)

When `+sve` is passed in the command line, if the Architecture being
targeted is V8.6A/V9.1A or later, `+f32mm` is also added. This enables
FEAT_32MM, however at the time of writing no CPU's support this. This
leads to the FEAT_32MM instructions being compiled for CPU's that do not
support them.

This commit removes the automatic enablement, however the option is
still able to be used by passing `+f32mm`.

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[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (#85401)

[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (#85401)

[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520AE:
https://developer.arm.com/documentation/107726/latest/

Technical Reference Manual for Cortex-A720AE:
https://developer.arm.com/documentation/102828/latest/

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Add support for Arm Cortex A78AE CPU (#84485)

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
https://developer.arm.com/documentation/101779/0003

Fixe

Add support for Arm Cortex A78AE CPU (#84485)

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
https://developer.arm.com/documentation/101779/0003

Fixes #84450

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[ARM][AArch64] Reformat target parser. NFC (#82601)

This is something we generally tend to avoid due to it confusing the git
history, but with the new github formatting bots being more noisy we
ke

[ARM][AArch64] Reformat target parser. NFC (#82601)

This is something we generally tend to avoid due to it confusing the git
history, but with the new github formatting bots being more noisy we
keep running into issues with the existing formatting when adding or
adjusting CPUs. This patch formats the code to make sure we are in a
good state going forward.

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[ARM][AArch64] Enable FEAT_FHM for Arm Neoverse N2 (#82613)

Correct an issue with Arm Neoverse N2 after it was
changed to a v9a core in change
f576cbe44eabb8a5ac0af817424a0d1e7c8fbf85:

* FEAT

[ARM][AArch64] Enable FEAT_FHM for Arm Neoverse N2 (#82613)

Correct an issue with Arm Neoverse N2 after it was
changed to a v9a core in change
f576cbe44eabb8a5ac0af817424a0d1e7c8fbf85:

* FEAT_FHM should be enabled for this core.

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