Revert "[globalisel][unittests] Rename setUp() to avoid potential mix up with SetUp() from gtest"

Forgot to apply commit message changes from phabricator

This reverts commit 3a016e31ecef7eeb876b540

Revert "[globalisel][unittests] Rename setUp() to avoid potential mix up with SetUp() from gtest"

Forgot to apply commit message changes from phabricator

This reverts commit 3a016e31ecef7eeb876b540c928a25a7c5d2e07a.

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[globalisel][unittests] Rename setUp() to avoid potential mix up with SetUp() from gtest

Also, make it structurally required so it can't be forgotten and re-introduce
the bug that led to the rotten

[globalisel][unittests] Rename setUp() to avoid potential mix up with SetUp() from gtest

Also, make it structurally required so it can't be forgotten and re-introduce
the bug that led to the rotten green tests.

Differential Revision: https://reviews.llvm.org/D99692

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[GlobalISel] Implement lowering for G_ROTR and G_ROTL.

This is a straightforward port.

Differential Revision: https://reviews.llvm.org/D99449

GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

It is good to have a combined `divrem` instruction when the
`div` and `rem` are computed from identical input operands.
Some targets can lower them

GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

It is good to have a combined `divrem` instruction when the
`div` and `rem` are computed from identical input operands.
Some targets can lower them through a single expansion that
computes both division and remainder. It effectively reduces
the number of instructions than individually expanding them.

Reviewed By: arsenm, paquette

Differential Revision: https://reviews.llvm.org/D96013

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GlobalISel: Merge and cleanup more AMDGPU call lowering code

This merges more AMDGPU ABI lowering code into the generic call
lowering. Start cleaning up by factoring away more of the pack/unpack
log

GlobalISel: Merge and cleanup more AMDGPU call lowering code

This merges more AMDGPU ABI lowering code into the generic call
lowering. Start cleaning up by factoring away more of the pack/unpack
logic into the buildCopy{To|From}Parts functions. These could use more
improvement, and the SelectionDAG versions are significantly more
complex, and we'll eventually have to emulate all of those cases too.

This is mostly NFC, but does result in some minor instruction
reordering. It also removes some of the limitations with mismatched
sizes the old code had. However, similarly to the merge on the input,
this is forcing gfx6/gfx7 to use the gfx8+ ABI (which is what we
actually want, but SelectionDAG is stuck using the weird emergent
ABI).

This also changes the load/store size for stack passed EVTs for
AArch64, which makes it consistent with the DAG behavior.

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[GlobalISel] Implement narrowScalar for SADDE/SSUBE/UADDE/USUBE

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96673

[GlobalISel] Implement narrowScalar for SADDO/SSUBO

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96672

[GlobalISel] Implement narrowScalar for UADDO/USUBO

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D96671

[RGT][GlobalIsel] Add missing setUp() calls to legalizer unittests

Some of these accidentally disabled tests failed as a result; updated
tests per @qcolombet instructions. A small number needed addi

[RGT][GlobalIsel] Add missing setUp() calls to legalizer unittests

Some of these accidentally disabled tests failed as a result; updated
tests per @qcolombet instructions. A small number needed additional
updates because legalization has actually changed since they were
written.

Found by the Rotten Green Tests project.

Differential Revision: https://reviews.llvm.org/D95257

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[GlobalISel] Implement widenScalar for carry-in add/sub

These are widened to a wider UADDE/USUBE, with the overflow value
unused, and with the same synthesis of a new overflow value as for the
O ope

[GlobalISel] Implement widenScalar for carry-in add/sub

These are widened to a wider UADDE/USUBE, with the overflow value
unused, and with the same synthesis of a new overflow value as for the
O operations.

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D95326

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Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method""

This reverts commit 554b3211fefd09b56b64357b9edd66c78ae200b5.

Differential Revision: https://reviews.llvm.org/D95

Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method""

This reverts commit 554b3211fefd09b56b64357b9edd66c78ae200b5.

Differential Revision: https://reviews.llvm.org/D95035

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Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method"

This reverts commit 2bb92bf451d7eb2c817f3e5403353e7c0c14d350.

Dependent patch broke UBSan on Android:
3dedad475da45c05bc4f

Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method"

This reverts commit 2bb92bf451d7eb2c817f3e5403353e7c0c14d350.

Dependent patch broke UBSan on Android:
3dedad475da45c05bc4f66cd14e9f44581edf0bc

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[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method

The widenScalar implementation for signed and unsigned overflowing
operations were very similar: both are checked by truncating the

[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method

The widenScalar implementation for signed and unsigned overflowing
operations were very similar: both are checked by truncating the result
and then re-sign/zero-extending it and checking that it matches the
computed operation.

Using a truncate + zero-extend for the unsigned case instead of manually
producing the AND instruction like before leads to an extra copy
instruction during legalization, but this should be harmless.

Differential Revision: https://reviews.llvm.org/D95035

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[GlobalISel] fix widenScalarUnmerge if widen type is not a multiple of destination type

Fix creation of illegal unmerge when widen was requested to a type which
is not a multiple of the destination

[GlobalISel] fix widenScalarUnmerge if widen type is not a multiple of destination type

Fix creation of illegal unmerge when widen was requested to a type which
is not a multiple of the destination type. E.g. when trying to widen
an s48 unmerge to s64 the existing code would create an illegal unmerge
from s64 to s48.

Instead, create further unmerges to a GCD type, then use this to remerge
these intermediate results to the actual destinations.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D88422

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GlobalISel: Use unmerge when copying wide vectors to result registers

Avoid using G_EXTRACT and move towards a more consistent vector
legalization strategy.

GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELT

Add unit tests since AMDGPU will only trigger this for gigantic
vectors, and won't use the annoying odd sized breakdown case.

GlobalISel: Reimplement moreElementsVectorDst

Use pad with undef and unmerge with unused results. This is annoyingly
similar to several other places in LegalizerHelper, but they're all
slightly diff

GlobalISel: Reimplement moreElementsVectorDst

Use pad with undef and unmerge with unused results. This is annoyingly
similar to several other places in LegalizerHelper, but they're all
slightly different.

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GlobalISel: Set instr/debugloc before any legalizer action

It was annoying enough that every custom lowering needed to set the
insert point, but this was made worse since now these all needed to be

GlobalISel: Set instr/debugloc before any legalizer action

It was annoying enough that every custom lowering needed to set the
insert point, but this was made worse since now these all needed to be
updated to setInstrAndDebugLoc. Consolidate these so every
legalization action has the right insert position by default.

This should fix dropping debug info in every custom AMDGPU
legalization.

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GlobalISel: Add G_EXTRACT/G_INSERT offset to legalize info

Immediate legalize fields were added for G_SEXT_INREG. Simiarly, these
are likely not legal except for certain offsets.

[GlobalISel][AMDGPU] add legalization for G_FREEZE

Summary:
Copy the legalization rules from SelectionDAG:
-widenScalar using anyext
-narrowScalar using intermediate merges
-scalarize/fewerElements

[GlobalISel][AMDGPU] add legalization for G_FREEZE

Summary:
Copy the legalization rules from SelectionDAG:
-widenScalar using anyext
-narrowScalar using intermediate merges
-scalarize/fewerElements using unmerge
-moreElements using G_IMPLICIT_DEF and insert

Add G_FREEZE legalization actions to AMDGPULegalizerInfo.
Use the same legalization actions as G_IMPLICIT_DEF.

Depends on D77795.

Reviewers: dsanders, arsenm, aqjune, aditya_nandakumar, t.p.northover, lebedev.ri, paquette, aemerson

Reviewed By: arsenm

Subscribers: kzhuravl, yaxunl, dstuttard, tpr, t-tye, jvesely, nhaehnle, kerbowa, wdng, rovka, hiraditya, volkan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78092

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[GlobalISel] support narrow G_IMPLICIT_DEF for DstSize % NarrowSize != 0

Summary:
When narrowing G_IMPLICIT_DEF where the original size is not a multiple
of the narrow size, emit a smaller G_IMPLICI

[GlobalISel] support narrow G_IMPLICIT_DEF for DstSize % NarrowSize != 0

Summary:
When narrowing G_IMPLICIT_DEF where the original size is not a multiple
of the narrow size, emit a smaller G_IMPLICIT_DEF and use G_ANYEXT.

To prevent a potential endless loop in the legalizer, the condition
to combine G_ANYEXT(G_IMPLICIT_DEF) is changed from isInstUnsupported
to !isInstLegal, since in this case the combine is only valid if
consequent legalization of the newly combined G_IMPLICIT_DEF does not
introduce G_ANYEXT due to narrowing.

Although this legalization for G_IMPLICIT_DEF would also be valid for
the general case, it actually caused a lot of code regressions when
tried due to superfluous COPYs and combines not getting hit anymore.

Reviewers: dsanders, aemerson, volkan, arsenm, aditya_nandakumar

Reviewed By: arsenm

Subscribers: jvesely, nhaehnle, kerbowa, wdng, rovka, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76598

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[Alignment][NFC] Use Align version of getMachineMemOperand

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llv

[Alignment][NFC] Use Align version of getMachineMemOperand

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jyknight, sdardis, nemanjai, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, jfb, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77059

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[GlobalISel] add helper function to create arbitrary libcalls

Summary:
The existing helper function can only create a libcall to functions available in
RTLIB. Add a helper function that can create a

[GlobalISel] add helper function to create arbitrary libcalls

Summary:
The existing helper function can only create a libcall to functions available in
RTLIB. Add a helper function that can create a libcall to a given function name
using the provided calling convention.

Reviewers: aditya_nandakumar, t.p.northover, rovka, arsenm, dsanders

Reviewed By: arsenm

Subscribers: wdng, hiraditya, volkan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76845

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GlobalISel: Introduce bitcast legalize action

For some operations, the type is unimportant and only the number of
bits matters. For example I don't want to treat <4 x s8> as a legal
type, but I also

GlobalISel: Introduce bitcast legalize action

For some operations, the type is unimportant and only the number of
bits matters. For example I don't want to treat <4 x s8> as a legal
type, but I also don't want to decompose loads of this into smaller
pieces to get legal register types.

On AMDGPU in SelectionDAG, we legalize a number of operations (most
notably load and store) by coercing all types to vectors of i32. For
GlobalISel, I'm trying very hard to avoid doing this for every type,
but I don't think this strategy can be completely avoided. I'm trying
to avoid bitcasts for any legitimately legal type we can operate on,
since the intervening bitcasts have proven to be a hassle.

For loads, I think I can get away without ever casting the result
type, and handling any arbitrary bitwidth during selection (I will
eventually want new tablegen support to help with this, rather than
having to add every possible type as legal). The unmerge required to
do anything with the value should expand to the expected shifts. This
is trickier for stores, since it would now require handling a wide
array of truncates during selection which I don't want.

Future potentially interesting case are for vector indexing, where
sub-dword type should be indexed in s32 pieces.

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GlobalISel: Prepare to allow other target unit tests

Currently all GlobalISel unittests use a hardcoded AArch64 target
machine. Factor this so I can write some for AMDGPU specific known
bits unittes

GlobalISel: Prepare to allow other target unit tests

Currently all GlobalISel unittests use a hardcoded AArch64 target
machine. Factor this so I can write some for AMDGPU specific known
bits unittests.

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