[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)

In accordance with https://github.com/llvm/llvm-project/issues/123569

In order to keep the patch at reasonable size, this

[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)

In accordance with https://github.com/llvm/llvm-project/issues/123569

In order to keep the patch at reasonable size, this PR only covers for
the llvm subproject, unittests excluded.

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[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

Convert many instances of:
Fn = Intrinsic::getOrInsertDeclaration(...);
CreateCall(Fn, ...)
to the equivalent CreateIntrinsi

[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)

Convert many instances of:
Fn = Intrinsic::getOrInsertDeclaration(...);
CreateCall(Fn, ...)
to the equivalent CreateIntrinsic call.

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[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)

Rename the function to reflect its correct behavior and to be consistent
with `Module::getOrInsertFunction`. This is a

[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)

Rename the function to reflect its correct behavior and to be consistent
with `Module::getOrInsertFunction`. This is also in preparation of
adding a new `Intrinsic::getDeclaration` that will have behavior similar
to `Module::getFunction` (i.e, just lookup, no creation).

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[InstCombine][X86] Only demand the active index bits for VPERMV/VPERMV3 mask values (#106750)

VPERMV/VPERMV3 only uses the lower bits of the vector element indices - so use SimplifyDemandedBits to i

[InstCombine][X86] Only demand the active index bits for VPERMV/VPERMV3 mask values (#106750)

VPERMV/VPERMV3 only uses the lower bits of the vector element indices - so use SimplifyDemandedBits to ignore anything touching the remaining bits.

Fixes #106413

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[X86] Rename trailing whitespace. NFC.

Noticed in clang-formatting of #106750

[InstCombine][X86] Only demand used bits for VPERMILPD/VPERMILPS mask values

VPERMILPS lower bits0-3 (to index per-lane i32/f32 0-3)
VPERMILPD uses bit1 (to index per-lane i64/f64 0-1)

Use Simplif

[InstCombine][X86] Only demand used bits for VPERMILPD/VPERMILPS mask values

VPERMILPS lower bits0-3 (to index per-lane i32/f32 0-3)
VPERMILPD uses bit1 (to index per-lane i64/f64 0-1)

Use SimplifyDemandedBits to ignore anything touching the remaining bits.

Part of #106413

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[InstCombine][X86] Only demand used bits for PSHUFB mask values (#106377)

(V)PSHUFB only uses the sign bit (for zeroing) and the lower 4 bits (to index per-lane byte 0-15) - so use SimplifyDemandedB

[InstCombine][X86] Only demand used bits for PSHUFB mask values (#106377)

(V)PSHUFB only uses the sign bit (for zeroing) and the lower 4 bits (to index per-lane byte 0-15) - so use SimplifyDemandedBits to ignore anything touching the remaining bits.

Fixes #106256

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Remove the `x86_mmx` IR type. (#98505)

It is now translated to `<1 x i64>`, which allows the removal of a bunch
of special casing.

This _incompatibly_ changes the ABI of any LLVM IR function wit

Remove the `x86_mmx` IR type. (#98505)

It is now translated to `<1 x i64>`, which allows the removal of a bunch
of special casing.

This _incompatibly_ changes the ABI of any LLVM IR function with
`x86_mmx` arguments or returns: instead of passing in mmx registers,
they will now be passed via integer registers. However, the real-world
incompatibility caused by this is expected to be minimal, because Clang
never uses the x86_mmx type -- it lowers `__m64` to either `<1 x i64>`
or `double`, depending on ABI.

This change does _not_ eliminate the SelectionDAG `MVT::x86mmx` type.
That type simply no longer corresponds to an IR type, and is used only
by MMX intrinsics and inline-asm operands.

Because SelectionDAGBuilder only knows how to generate the
operands/results of intrinsics based on the IR type, it thus now
generates the intrinsics with the type MVT::v1i64, instead of
MVT::x86mmx. We need to fix this before the DAG LegalizeTypes, and thus
have the X86 backend fix them up in DAGCombine. (This may be a
short-lived hack, if all the MMX intrinsics can be removed in upcoming
changes.)

Works towards issue #98272.

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[InstCombine][X86] Peek through bitcast+shuffle+bitcast sequence when folding BLENDV to SELECT

Mentioned on #96882

[InstCombine][X86] Pull out repeated uses of PatternMatch namespace. NFC.

Followup requested on #96882

[InstCombine][X86] Add multiply-by-one handling for MULH/PMULHU/PMULHRS intrinsics

MULH/PMULHU simplifies to ASHR/ZERO as they just become a SEXT/ZEXT sign-splat instruction

PMULHRS doesn't simplif

[InstCombine][X86] Add multiply-by-one handling for MULH/PMULHU/PMULHRS intrinsics

MULH/PMULHU simplifies to ASHR/ZERO as they just become a SEXT/ZEXT sign-splat instruction

PMULHRS doesn't simplify as much so I've not attempted to fold it.

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[InstCombine][X86] Add constant folding for PMULH/PMULHU/PMULHRS intrinsics

[InstCombine][X86] Add zero/undef arg handling for MULH/PMULHU/PMULHRS intrinsics

[InstCombine][X86] simplifyDemandedVectorEltsIntrinsic - add handling for PMULH/PMULHU/PMULHRS intrinsics

Fix signed/unsigned integer comparison warning. NFC.

[InstCombine][X86] Fold blendv(x,y,shuffle(bitcast(sext(m)))) -> select(shuffle(m),x,y) (#96882)

We already handle blendv(x,y,bitcast(sext(m))) -> select(m,x,y) cases, but this adds support for peek

[InstCombine][X86] Fold blendv(x,y,shuffle(bitcast(sext(m)))) -> select(shuffle(m),x,y) (#96882)

We already handle blendv(x,y,bitcast(sext(m))) -> select(m,x,y) cases, but this adds support for peeking through one-use shuffles as well. VectorCombine should already have canonicalized the IR to shuffle(bitcast(...)) for us.

The particular use case is where we have split generic 256/512-bit code to use target-specific blendv intrinsics (e.g. AVX1 spoofing AVX2 256-bit ops).

Fixes #58895

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[InstCombine][X86] Fold avx512 vpermi2 intrinsics with constant masks to generic shuffles

Similar to most other x86 shuffles, if the shuffle mask is constant then convert to a generic shuffle

[InstCombine][X86] Add undef arg handling for PMADDWD/PMADDUBSW intrinsics

These fold to zero, not undef, as the other arg could still be zero.

[InstCombine][X86] Add constant folding for PMADDWD/PMADDUBSW intrinsics

[InstCombine][X86] Add zero arg handling for PMADDWD/PMADDUBSW intrinsics

PMADDWD/PMADDUBSW - multiply by zero folds

Initial setup to handle future PMADDWD/PMADDUBSW simplification / constant foldi

[InstCombine][X86] Add zero arg handling for PMADDWD/PMADDUBSW intrinsics

PMADDWD/PMADDUBSW - multiply by zero folds

Initial setup to handle future PMADDWD/PMADDUBSW simplification / constant folding

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[InstCombine][X86] simplifyDemandedVectorEltsIntrinsic - add handling for PMADDWD/PMADDUBSW intrinsics

[IR] Add getDataLayout() helpers to BasicBlock and Instruction (#96902)

This is a helper to avoid writing `getModule()->getDataLayout()`. I
regularly try to use this method only to remember it does

[IR] Add getDataLayout() helpers to BasicBlock and Instruction (#96902)

This is a helper to avoid writing `getModule()->getDataLayout()`. I
regularly try to use this method only to remember it doesn't exist...

`getModule()->getDataLayout()` is also a common (the most common?)
reason why code has to include the Module.h header.

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[InstCombine][X86] Avoid repeated getType() calls when folding blendv->select. NFC.

Cleanup prep work for #58895

Replace uses of ConstantExpr::getCompare. (#91558)

Use ICmpInst::compare() where possible, ConstantFoldCompareInstOperands
in other places. This only changes places where the either the fold is
gu

Replace uses of ConstantExpr::getCompare. (#91558)

Use ICmpInst::compare() where possible, ConstantFoldCompareInstOperands
in other places. This only changes places where the either the fold is
guaranteed to succeed, or the code doesn't use the resulting compare if
we fail to fold.

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[X86][InstCombine] Avoid -Wparentheses warnings introduced in D145220, NFCI