History log of /llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp (Results 201 – 210 of 210)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
# 9099b5e6 16-Sep-2015 Hans Wennborg <hans@hanshq.net>

Try to fix WebAssembly build after r247864

llvm-svn: 247870


# 950a13cf 16-Sep-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Check in an initial CFG Stackifier pass

This pass implements a simple algorithm for conversion from CFG to
wasm's structured control flow. It doesn't yet handle multiple-entry
loops; t

[WebAssembly] Check in an initial CFG Stackifier pass

This pass implements a simple algorithm for conversion from CFG to
wasm's structured control flow. It doesn't yet handle multiple-entry
loops; that will be added in a future patch.

It also adds initial support for switch statements.

Differential Revision: http://reviews.llvm.org/D12735

llvm-svn: 247818

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# e32c5744 08-Sep-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Support running without a register allocator in the default CodeGen passes

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other pas

[WebAssembly] Support running without a register allocator in the default CodeGen passes

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

llvm-svn: 247065

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# 25d2a0dd 08-Sep-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Enable SSA lowering and other pre-regalloc passes

llvm-svn: 247008


Revision tags: llvmorg-3.7.0, llvmorg-3.7.0-rc4, llvmorg-3.7.0-rc3
# dde8dce6 19-Aug-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Use the default alignment for SIMD types.

Previously WebAssembly's datalayout string had -v128:8:128. This had been an
attempt to declare a certain level of support for unaligned SIMD

[WebAssembly] Use the default alignment for SIMD types.

Previously WebAssembly's datalayout string had -v128:8:128. This had been an
attempt to declare a certain level of support for unaligned SIMD accesses.
However, clang makes its own determinations for SIMD alignment that are
independent of the datalayout string, so this wasn't actually meaningful.

llvm-svn: 245494

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Revision tags: studio-1.4
# 3adc7ce9 11-Aug-2015 Rafael Espindola <rafael.espindola@gmail.com>

Use llvm::make_unique to fix the MSVC build.

llvm-svn: 244641


# 600aee98 31-Jul-2015 JF Bastien <jfb@google.com>

WebAssembly: print basic integer assembly.

Summary:
This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats:

- The operation names are cur

WebAssembly: print basic integer assembly.

Summary:
This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats:

- The operation names are currently incorrect.
- Other integer and floating-point types will be added later.
- The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways.
- The assembly format isn't full s-expressions yet either, this will be added later.
- This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11671

llvm-svn: 243763

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Revision tags: llvmorg-3.7.0-rc2, llvmorg-3.7.0-rc1
# 03855df1 01-Jul-2015 JF Bastien <jfb@google.com>

WebAssembly: start instructions

Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic proc

WebAssembly: start instructions

Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

llvm-svn: 241211

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# d82494bb 01-Jul-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Define separate Target instances for 32-bit and 64-bit.

llvm-svn: 241193


# 10e730a2 29-Jun-2015 Dan Gohman <dan433584@gmail.com>

[WebAssembly] Initial WebAssembly backend

This WebAssembly backend is just a skeleton at this time and is not yet
functional.

llvm-svn: 241022


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