Revision tags: llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2 |
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#
05640657 |
| 25-Sep-2023 |
Paulo Matos <pmatos@igalia.com> |
[SPIRV] Implement support for SPV_KHR_expect_assume (#66217)
Adds new extension SPV_KHR_expect_assume, new capability
ExpectAssumeKHR as well as the new instructions:
* OpExpectKHR
* OpAssume
[SPIRV] Implement support for SPV_KHR_expect_assume (#66217)
Adds new extension SPV_KHR_expect_assume, new capability
ExpectAssumeKHR as well as the new instructions:
* OpExpectKHR
* OpAssumeTrueKHR
These are lowered from respectively llvm.expect.<ty> and llvm.assume
intrinsics.
Previously https://reviews.llvm.org/D157696
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e7651e60 |
| 22-Sep-2023 |
Paulo Matos <pmatos@igalia.com> |
[SPIRV] Add support for SPV_KHR_bit_instructions (#66215)
Adds support for SPV_KHR_bit_instructions.
It is only used whenever we don't need the whole Shader capability, which is a superset of thi
[SPIRV] Add support for SPV_KHR_bit_instructions (#66215)
Adds support for SPV_KHR_bit_instructions.
It is only used whenever we don't need the whole Shader capability, which is a superset of this extension.
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#
116f7a2d |
| 19-Sep-2023 |
Natalie Chouinard <1953083+sudonatalie@users.noreply.github.com> |
[SPIRV] Test basic float and int types (#66282)
Add Int16, Int64 and Float64 capabilities as always available for Vulkan
(since 1.0), and add tests covering most of the basic types from
clang/test
[SPIRV] Test basic float and int types (#66282)
Add Int16, Int64 and Float64 capabilities as always available for Vulkan
(since 1.0), and add tests covering most of the basic types from
clang/test/CodeGenHLSL/basic_types.hlsl except for half floats.
Depends on D156049
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Revision tags: llvmorg-17.0.1, llvmorg-17.0.0 |
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#
efe0e107 |
| 06-Sep-2023 |
Michal Paszkowski <michal.paszkowski@outlook.com> |
[SPIR-V] Support SPV_INTEL_arbitrary_precision_integers_extension, misc utils for other extensions
Differential Revision: https://reviews.llvm.org/D158764
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Revision tags: llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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#
56396b25 |
| 24-Jul-2023 |
Nathan Gauër <brioche@google.com> |
[SPIRV-V] Add SPIR-V logical triple to llc
This commits adds the minimal required bits to build a logical SPIR-V compute shader using LLC. - Skip OpenCL-only capabilities & extensions for Logical SP
[SPIRV-V] Add SPIR-V logical triple to llc
This commits adds the minimal required bits to build a logical SPIR-V compute shader using LLC. - Skip OpenCL-only capabilities & extensions for Logical SPIR-V. - Generate required metadata for entrypoints from HLSL frontend. - Fix execution mode to GLCompute in logical.
The main issue is the lack of "vulkan" bit in the triple. This might need to be added as a vendor? Because as-is, SPIRV32/64 assumes OpenCL, and then, SPIRV assumes Vulkan. This is ok-ish today, but not correct.
Differential Revision: https://reviews.llvm.org/D156424
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8f3b87fc |
| 26-Jul-2023 |
Paulo Matos <pmatos@igalia.com> |
[SPIRV] Add support for SPV_INTEL_optnone
Adds support for SPV_INTEL_optnone.
Currently still in draft form but I wanted to open this revision to ask some questions.
Differential Revision: https:/
[SPIRV] Add support for SPV_INTEL_optnone
Adds support for SPV_INTEL_optnone.
Currently still in draft form but I wanted to open this revision to ask some questions.
Differential Revision: https://reviews.llvm.org/D156297
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1 |
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8bfb2b6d |
| 26-Mar-2023 |
Michal Paszkowski <michal.paszkowski@outlook.com> |
[SPIR-V] Remove switch G_ICMP+G_BRCOND+G_BR before ISel
IRTranslator lowers switches to [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. Since values and destination MBBs are included in the spv_switch
[SPIR-V] Remove switch G_ICMP+G_BRCOND+G_BR before ISel
IRTranslator lowers switches to [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. Since values and destination MBBs are included in the spv_switch intrinsics, the sequences are not needed for ISel.
Before this commit, the information decoded by these sequences were added to spv_switch intrinsics in SPIRVPreLegalizer and the sequences were kept until SPIRVModuleAnalysis where they were marked skipped for emission.
After this commit, the [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences and MBBs containing only these MIs are erased in SPIRVPreLegalizer.
Differential Revision: https://reviews.llvm.org/D146923
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Revision tags: llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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#
99203241 |
| 07-Jan-2023 |
Michal Paszkowski <michal.paszkowski@outlook.com> |
[SPIR-V] Map IR function pointers to registers in ModuleAnalysis
SPIRVModuleAnalysis collects module and external function registers (usually result of OpFunction) for use when emitting OpFunctionCa
[SPIR-V] Map IR function pointers to registers in ModuleAnalysis
SPIRVModuleAnalysis collects module and external function registers (usually result of OpFunction) for use when emitting OpFunctionCall. This patch makes the mapping between the functions and registers using pointers (instead of name strings) to ensure anonymous functions and calls can be resolved properly.
Differential Revision: https://reviews.llvm.org/D140548
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3 |
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#
7a3c9a85 |
| 06-Oct-2022 |
Michal Paszkowski <michal.paszkowski@outlook.com> |
[SPIRV] Fix call lowering of "anonymous" functions
The patch fixes lowering of anonymous functions, removes file/linkage info for builtin call demangling, and adds relevant test demonstrating a fixe
[SPIRV] Fix call lowering of "anonymous" functions
The patch fixes lowering of anonymous functions, removes file/linkage info for builtin call demangling, and adds relevant test demonstrating a fixed problem.
Differential Revision: https://reviews.llvm.org/D135390
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Revision tags: working, llvmorg-15.0.2, llvmorg-15.0.1 |
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#
3544d200 |
| 14-Sep-2022 |
Ilia Diachkov <ilia.diachkov@gmail.com> |
[SPIRV] add IR regularization pass
The patch adds the regularization pass that prepare LLVM IR for the IR translation. It also contains following changes: - reduce indentation, make getNonParametriz
[SPIRV] add IR regularization pass
The patch adds the regularization pass that prepare LLVM IR for the IR translation. It also contains following changes: - reduce indentation, make getNonParametrizedType, getSamplerType, getPipeType, getImageType, getSampledImageType static in SPIRVBuiltins, - rename mayBeOclOrSpirvBuiltin to getOclOrSpirvBuiltinDemangledName, - move isOpenCLBuiltinType, isSPIRVBuiltinType, isSpecialType from SPIRVGlobalRegistry.cpp to SPIRVUtils.cpp, renaming isSpecialType to isSpecialOpaqueType, - implment getTgtMemIntrinsic() in SPIRVISelLowering, - add hasSideEffects = 0 in Pseudo (SPIRVInstrFormats.td), - add legalization rule for G_MEMSET, correct G_BRCOND rule, - add capability processing for OpBuildNDRange in SPIRVModuleAnalysis, - don't correct types of registers holding constants and used in G_ADDRSPACE_CAST (SPIRVPreLegalizer.cpp), - lower memset/bswap intrinsics to functions in SPIRVPrepareFunctions, - change TargetLoweringObjectFileELF to SPIRVTargetObjectFile in SPIRVTargetMachine.cpp, - correct comments. 5 LIT tests are added to show the improvement.
Differential Revision: https://reviews.llvm.org/D133253
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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Revision tags: llvmorg-15.0.0, llvmorg-15.0.0-rc3 |
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#
f61eb416 |
| 23-Aug-2022 |
Ilia Diachkov <ilia.diachkov@gmail.com> |
[SPIRV] support builtin functions
The patch adds support for OpenCL and SPIR-V built-in functions. Their detection and properties are implemented using TableGen. Five tests are added to demonstrate
[SPIRV] support builtin functions
The patch adds support for OpenCL and SPIR-V built-in functions. Their detection and properties are implemented using TableGen. Five tests are added to demonstrate the improvement.
Differential Revision: https://reviews.llvm.org/D132024
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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#
796124f0 |
| 23-Aug-2022 |
Michael Liao <michael.hliao@gmail.com> |
[SPIRV] Fix the wrong patch from https://reviews.llvm.org/D131886
- The body of that predicate lambda is removed by mistake.
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#
9181ab92 |
| 23-Aug-2022 |
liqinweng <Liqin.Weng@streamcomputing.com> |
[NFC]] Use llvm::all_of instead of std::all_of
Reviewed By: kazu
Differential Revision: https://reviews.llvm.org/D131886
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#
df871307 |
| 10-Aug-2022 |
Ilia Diachkov <ilia.diachkov@gmail.com> |
[SPIRV] support capabilities and extensions
This patch supports SPIR-V capabilities and extensions. In addition, it inserts decorations related to MIFlags and improves support of switches. Five test
[SPIRV] support capabilities and extensions
This patch supports SPIR-V capabilities and extensions. In addition, it inserts decorations related to MIFlags and improves support of switches. Five tests are included to demonstrate the improvement.
Differential Revision: https://reviews.llvm.org/D131221
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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Revision tags: llvmorg-15.0.0-rc2 |
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#
b25b507c |
| 01-Aug-2022 |
Ilia Diachkov <ilia.diachkov@gmail.com> |
[SPIRV] use tablegen to create SPIRVBaseInfo*
The patch replaces SPIRVBaseInfo.* previously created using macros by the tablegen approach. There are many small changes in other files due to differen
[SPIRV] use tablegen to create SPIRVBaseInfo*
The patch replaces SPIRVBaseInfo.* previously created using macros by the tablegen approach. There are many small changes in other files due to differences in namespaces. Also, functions in SPIRVUtils are moved to the llvm namespace.
Differential Revision: https://reviews.llvm.org/D130518
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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Revision tags: llvmorg-15.0.0-rc1, llvmorg-16-init |
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#
b8e1544b |
| 20-Jul-2022 |
Ilia Diachkov <iliya.diyachkov@intel.com> |
[SPIRV] add SPIRVPrepareFunctions pass and update other passes
The patch adds SPIRVPrepareFunctions pass, which modifies function signatures containing aggregate arguments and/or return values befor
[SPIRV] add SPIRVPrepareFunctions pass and update other passes
The patch adds SPIRVPrepareFunctions pass, which modifies function signatures containing aggregate arguments and/or return values before IR translation. Information about the original signatures is stored in metadata. It is used during call lowering to restore correct SPIR-V types of function arguments and return values. This pass also substitutes some llvm intrinsic calls to function calls, generating the necessary functions in the module, as the SPIRV translator does.
The patch also includes changes in other modules, fixing errors and enabling many SPIR-V features that were omitted earlier. And 15 LIT tests are also added to demonstrate the new functionality.
Differential Revision: https://reviews.llvm.org/D129730
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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Revision tags: llvmorg-14.0.6 |
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#
fa2a7a25 |
| 18-Jun-2022 |
Aleksandr Bezzubikov <zuban32s@gmail.com> |
[SPIR-V] Introduce SPIR-V global entities tracking and deduplication infra.
SPIR-V module typically contains some global entities that were not global before made it to SPIR-V, e.g. types and consta
[SPIR-V] Introduce SPIR-V global entities tracking and deduplication infra.
SPIR-V module typically contains some global entities that were not global before made it to SPIR-V, e.g. types and constants are not usually declared globally in LLVM. By design SPIR-V requires such stuff to be declared once and in the module's global section. Since MIR is not able to represent such things properly they were generated per-function, and then at the very end of the backend's pipeline hoisted into some 'meta' function minding possible duplicates.
New SPIRVDuplicatesTracker keeps mapping of the original LLVM entities such as types, constant, global variables, etc to their MIR counterparts - (MachineFunction, Register). Later SPIRVModuleAnalysis (apart from other thing it's responsible for) performs topological sorting of the tracker's entries to ensure proper ordering before the hoisting, and actually performs the hoisting in a duplicates-free manner by the tracker's nature.
Differential Revision: https://reviews.llvm.org/D128471
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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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#
153dee34 |
| 14-Apr-2022 |
Ilia Diachkov <iliya.diyachkov@intel.com> |
[SPIR-V](6/6) Add the module analysis pass and the simplest tests
This patch adds one SPIRV analysis pass and extends AsmPrinter. It is essential for minimum SPIR-V output. Also it adds several simp
[SPIR-V](6/6) Add the module analysis pass and the simplest tests
This patch adds one SPIRV analysis pass and extends AsmPrinter. It is essential for minimum SPIR-V output. Also it adds several simplest tests to show that the target basically works.
Differential Revision: https://reviews.llvm.org/D116465
Authors: Aleksandr Bezzubikov, Lewis Crawford, Ilia Diachkov, Michal Paszkowski, Andrey Tretyakov, Konrad Trifunovic
Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Co-authored-by: Ilia Diachkov <iliya.diyachkov@intel.com> Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com> Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com> Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>
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