Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:

_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr

instead of:

_

Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:

_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr

instead of:

_test_rol:
mfvrsave r2, 256
mr r3, r2
mtvrsave r3
vspltisw v2, -12
vrlw v2, v2, v2
mtvrsave r2
blr

Testcase here: CodeGen/PowerPC/vec_vrsave.ll

llvm-svn: 27777

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Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:

_test_rol:
mfspr r2, 256
mr r3

Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:

_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr

instead of:

_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr

llvm-svn: 27772

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Move some knowledge about registers out of the code emitter into the register info.

llvm-svn: 27770

Use a small table instead of macros to do this conversion.

llvm-svn: 27769

Fix SingleSource/UnitTests/Vector/sumarray-dbl

llvm-svn: 27594

Fix PR727, correctly handling large stack aligments on ppc

llvm-svn: 27593

Suppress debug label when not debug.

llvm-svn: 27588

Foundation for call frame information.

llvm-svn: 27491

Force use of a frame-pointer if there is anything on the stack that is aligned
more than the OS keeps the stack aligned.

llvm-svn: 27381

Expose base register for DwarfWriter. Refactor code accordingly.

llvm-svn: 27225

Translate llvm target registers to dwarf register numbers properly.

llvm-svn: 27180

Add support to locate local variables in frames (early version.)

llvm-svn: 26994

When possible, custom lower 32-bit SINT_TO_FP to this:

_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr

instead of this

When possible, custom lower 32-bit SINT_TO_FP to this:

_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr

instead of this:

_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943

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remove dead variable

llvm-svn: 26813

teach the ppc backend how to spill/reload vector regs

llvm-svn: 26806

in functions that use a lot of callee saved regs, this can be more than
5 instructions away.

llvm-svn: 26801

Add support for copying registers. still needed: spilling and reloading them

llvm-svn: 26800

For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c

For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}

to this:

_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr

GCC produces this (which has additional stack accesses):

_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr

llvm-svn: 26733

show more ...

Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913

Fix an off-by-one error that Nate's eagle eyes caught

llvm-svn: 25231

Use the auto-insert BuildMI constructor to avoid an explicit insert. No
functionality change, just code cleanup.

llvm-svn: 25230

If a function has a non-zero sized frame, use an add to adjust the stack
pointer in the epilog, not a load.

llvm-svn: 25229

New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
hasInFlag, hasOutFlag.

llvm-svn: 25155

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag oper

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)

llvm-svn: 24997

show more ...

Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the

Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224

show more ...