Fix a crash on invalid code due to memcpy lowering.

llvm-svn: 44378

Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056

Completely forgot, that we have some debug information emission on PPC. This should fix
some regressions on ppc nightly tests.

llvm-svn: 44029

Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Ple

Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997

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- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.

llvm-svn: 43153

Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.

llvm-svn: 43150

Fix a bug handling frame references in ppc inline asm when the frame offset
doesn't fit into 16 bits.

llvm-svn: 43032

- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separ

- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621

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Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!

llvm-svn: 42346

Fix comments.

llvm-svn: 41947

Add missing index versions of instructions to the map.

llvm-svn: 41776

Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the ch

Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

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Long live the exception handling!

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and

Long live the exception handling!

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

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eliminateFrameIndex() change.

llvm-svn: 36626

Match MachineFunction::UsedPhysRegs changes.

llvm-svn: 36452

The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF t

The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.

llvm-svn: 35624

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Addition to the previous commit for getCalleeSavedRegClasses:

"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."

llvm-svn: 35623

The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.

llvm-svn: 35622

Protect R31's frame offset from being used by callee-saved registers, when R31
is the frame pointer.

llvm-svn: 35233

Added MRegisterInfo hook to re-materialize an instruction.

llvm-svn: 35205

Minor interface change.

llvm-svn: 34967

PEI now passes a RegScavenger ptr to eliminateFrameIndex.

llvm-svn: 34707

Duplicate use of LR, take 2.

llvm-svn: 34666

Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.

Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29

llvm-svn: 34652

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implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!

llvm-svn: 34574