Removed spurious EnablePPCRS check.

llvm-svn: 47918

Use a command-line option to turn register scavenging on/off for PPC.

llvm-svn: 47915

This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the defau

This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863

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Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR.

llvm-svn: 47067

Rename MRegisterInfo to TargetRegisterInfo.

llvm-svn: 46930

Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this sp

Remove the nasty LABEL hack with a much less evil one. Now llvm.dbg.func.start implies a stoppoint is set. SelectionDAGISel records a new source line but does not create a ISD::LABEL node for this special stoppoint. Asm printer will magically print this label. This ensures nothing is emitted before.

llvm-svn: 46635

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Add an extra operand to LABEL nodes which distinguishes between debug, EH, or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution.

llvm-svn: 46609

Makes the same change in ppc backend: avoid inserting prologue before debug labels.

llvm-svn: 46596

rename MachineInstr::setInstrDescriptor -> setDesc

llvm-svn: 45871

rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor

llvm-svn: 45680

Move even more functionality from MRegisterInfo into TargetInstrInfo.

Some day I'll get it all moved over...

llvm-svn: 45672

Move some more instruction creation methods from RegisterInfo into InstrInfo.

llvm-svn: 45484

Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470

Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
m

Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467

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Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should jus

Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464

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Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm

llvm-svn: 45453

Remove attribution from file headers, per discussion on llvmdev.

llvm-svn: 45418

Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:

_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr

inste

Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:

_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr

instead of:

_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr

for:

void foo(void **X) {
*X = __builtin_return_address(0);
}

on ppc64.

llvm-svn: 44701

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implement __builtin_return_addr(0) on ppc.

llvm-svn: 44700

refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.

llvm-svn: 44699

Fix a compilation warning.

llvm-svn: 44691

Added canFoldMemoryOperand for PPC.

llvm-svn: 44623

Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.

llvm-svn: 44600

Remove redundant foldMemoryOperand variants and other code clean up.

llvm-svn: 44517