Simplify code, NFC.

llvm-svn: 238750

Pass MCSymbols to the helper functions in MCELF.h.

llvm-svn: 238596

Pass a MCSymbol to needsRelocateWithSymbol.

llvm-svn: 238589

Remove a trivial forwarding function. NFC.

llvm-svn: 238506

Use raw_pwrite_stream in the object writer/streamer.

The ELF object writer will take advantage of that in the next commit.

llvm-svn: 234950

Re-enable target-specific relocation table sorting and use it for Mips

Some targets (ie. Mips) have additional rules for ordering the relocation
table entries. Allow them to override generic sortRel

Re-enable target-specific relocation table sorting and use it for Mips

Some targets (ie. Mips) have additional rules for ordering the relocation
table entries. Allow them to override generic sortRelocs(), which sorts
entries by Offset.
Then override this function for Mips, to emit HI16 and GOT16 relocations
against the local symbol in pair with the corresponding LO16 relocation.

Patch by Vladimir Stefanovic.

Differential Revision: http://reviews.llvm.org/D7414

llvm-svn: 234883

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Use 'override/final' instead of 'virtual' for overridden methods

The patch is generated using clang-tidy misc-use-override check.

This command was used:

tools/clang/tools/extra/clang-tidy/tool/r

Use 'override/final' instead of 'virtual' for overridden methods

The patch is generated using clang-tidy misc-use-override check.

This command was used:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \
-checks='-*,misc-use-override' -header-filter='llvm|clang' \
-j=32 -fix -format

http://reviews.llvm.org/D8925

llvm-svn: 234679

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[mips] Simplify boolean expressions in Mips target with `clang-tidy`

No functional changes.

Patch by Richard Thomson.

Differential Revision: http://reviews.llvm.org/D8522

llvm-svn: 233065

Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the

Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there.

llvm-svn: 232165

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[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226657

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Reverted revision 226577.

llvm-svn: 226595

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real

[mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B

Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226577

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[mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions

Differential Revision: http://reviews.llvm.org/D5271

llvm-svn: 225627

[mips][microMIPS] Relocate with symbol for micromips symbols
Differential Revision: http://reviews.llvm.org/D6796

llvm-svn: 225008

test commit (spelling correction)

llvm-svn: 223758

[MC] Pass MCSymbolData to needsRelocateWithSymbol

As discussed in a previous checking to support the .localentry
directive on PowerPC, we need to inspect the actual target symbol
in needsRelocateWit

[MC] Pass MCSymbolData to needsRelocateWithSymbol

As discussed in a previous checking to support the .localentry
directive on PowerPC, we need to inspect the actual target symbol
in needsRelocateWithSymbol to make the appropriate decision based
on that symbol's st_other bits.

Currently, needsRelocateWithSymbol does not get the target symbol.
However, it is directly available to its sole caller. This patch
therefore simply extends the needsRelocateWithSymbol by a new
parameter "const MCSymbolData &SD", passes in the target symbol,
and updates all derived implementations.

In particular, in the PowerPC implementation, this patch removes
the FIXME added by the previous checkin.

llvm-svn: 213487

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[mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890

llvm-svn: 210908

[mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866

llvm-svn: 210773

[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860

llvm-svn: 209659

[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824

llvm-svn: 209655

Don't relocate with sections if there might be a paired relocation.

llvm-svn: 205240

Completely rewrite ELFObjectWriter::RecordRelocation.

I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it h

Completely rewrite ELFObjectWriter::RecordRelocation.

I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
requiring a quiet nasty work around in ARM.
* It was missing comments.

llvm-svn: 205076

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Remove another unused argument.

llvm-svn: 204961

Remove unused argument.

llvm-svn: 204956

Support for microMIPS TLS relocations.

llvm-svn: 197685