[Hexagon] Handle out-of-range offsets in eliminateFrameIndex

Create a virtual register that will hold the actual address and use it
with the offset of 0 in the place of the original FI.

llvm-svn: 2

[Hexagon] Handle out-of-range offsets in eliminateFrameIndex

Create a virtual register that will hold the actual address and use it
with the offset of 0 in the place of the original FI.

llvm-svn: 260688

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[Hexagon] Mark D14 and GP as reserved registers

llvm-svn: 257336

[Hexagon] Add PIC support

llvm-svn: 256025

[Hexagon] Fix debug information for local objects

- Isolate the check for the existence of a stack frame into hasFP.
- Implement getFrameIndexReference for DWARF address computation.
- Use getFrameI

[Hexagon] Fix debug information for local objects

- Isolate the check for the existence of a stack frame into hasFP.
- Implement getFrameIndexReference for DWARF address computation.
- Use getFrameIndexReference for offset computation in eliminateFrameIndex.
- Preserve debug information for dynamically allocated stack objects.
- Prefer FP to access local objects at -O0.
- Add experimental code to skip allocframe when not strictly necessary
(disabled by default).

llvm-svn: 250718

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[Hexagon] Adding skeleton of HVX extension instructions.

llvm-svn: 250600

Targets: commonize some stack realignment code

This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`,

Targets: commonize some stack realignment code

This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.

Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.

The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.

The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.

`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11160

llvm-svn: 242727

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Target RegisterInfo: devirtualize TargetFrameLowering

Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast.

Target RegisterInfo: devirtualize TargetFrameLowering

Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can.

This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here.

Subscribers: sunfish, ted, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11093

llvm-svn: 241921

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[Hexagon] Overhaul of stack object allocation

- Use static allocation for aligned stack objects.
- Simplify dynamic stack object allocation.
- Simplify elimination of frame-indices.

llvm-svn: 235521

Remove unused complex patterns for addressing modes on Hexagon.

llvm-svn: 232057

Remove subtarget dependence from HexagonRegisterInfo.

llvm-svn: 231887

[Hexagon] Removing more V4 predicates since V4 is the required minimum.

llvm-svn: 228614

[Hexagon] Renaming A2_addi and formatting.

llvm-svn: 228318

[Hexagon] Replacing old versions of stores and loads.

llvm-svn: 226065

[Hexagon] Replacing old version of convert and load f64.

llvm-svn: 226057

[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.

llvm-svn: 224952

[Hexagon] Adding doubleword load.

llvm-svn: 224787

[Hexagon] Reapplying 224775 load words.

llvm-svn: 224786

Reverting 224775 until mayLoad flag is addressed.

llvm-svn: 224783

[Hexagon] Adding word loads.

llvm-svn: 224775

[Hexagon] Adding signed halfword loads.

llvm-svn: 224774

[Hexagon] Adding unsigned halfword load.

llvm-svn: 224772

[Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.

llvm-svn: 224735

[Hexagon] Adding classes and load unsigned byte instruction, updating usages.

llvm-svn: 224730

[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
Adding test to show correct instruction selection and encoding.

llvm-svn: 222249

Have MachineFunction cache a pointer to the subtarget to make lookups
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lo

Have MachineFunction cache a pointer to the subtarget to make lookups
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

llvm-svn: 214838

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