LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that

LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16. Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354

show more ...

Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assemb

Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.

llvm-svn: 125127

show more ...

Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.

llvm-svn: 121082

Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.

llvm-svn: 120589

Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allow

Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481

show more ...

Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.

llvm-svn: 118152

Detabify and clean up 80 column violations.

llvm-svn: 116454

Add ARM Disassembler to the CMake build.

llvm-svn: 114949

ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.

llvm-svn: 113345

The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encodin

The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894

show more ...

Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792.

llvm-svn: 110875

For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8

For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915

show more ...

More IT instruction error-handling improvements from fuzzing.

llvm-svn: 101839

Better error handling of invalid IT mask '0000', instead of just asserting.

llvm-svn: 101827

Fixed logic error. Should check Builder for validity before calling SetSession
on it.

llvm-svn: 101563

Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.

Since get

Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()
was asserting because the (RegClass, RegNum) combination doesn't make sense from
an encoding point of view.

Since getRegisterEnum() is used all over the place, to change the code to check
for encoding error after each call would not only bloat the code, but also make
it less readable. An Err flag is added to the ARMBasicMCBuilder where a client
can set a non-zero value to indicate some kind of error condition while building
up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false
if a non-zero value is detected.

llvm-svn: 101290

show more ...

Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it us

Fixed a nasty layering violation in the edis source
code. It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis. If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.

llvm-svn: 101179

show more ...

Get rid of traling whitespaces. No functionality change.

llvm-svn: 100404

The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)

to read 4 bytes of memory contents into

The disassembler impl. of MCDisassembler::getInstruction() was using the pattern
uint32_t insn;
MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL)

to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the
interpretation of byte order up to the host machine and causes PPC test cases of
arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for
reading the memory contents and shift the bytes into place for the 32-bit uint
variable in the ARM case and 16-bit halfword in the Thumb case.

llvm-svn: 100403

show more ...

Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invok

Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233

show more ...

Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the d

Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num. For example,

; CHECK: ldr.w r9, [r7, #28]

llvm-svn: 98637

show more ...