[ARM GlobalISel] Support G_CTLZ and G_CTLZ_ZERO_UNDEF

We can now select CLZ via the TableGen'erated code, so support G_CTLZ
and G_CTLZ_ZERO_UNDEF throughout the pipeline for types <= s32.

Legalizer

[ARM GlobalISel] Support G_CTLZ and G_CTLZ_ZERO_UNDEF

We can now select CLZ via the TableGen'erated code, so support G_CTLZ
and G_CTLZ_ZERO_UNDEF throughout the pipeline for types <= s32.

Legalizer:
If the CLZ instruction is available, use it for both G_CTLZ and
G_CTLZ_ZERO_UNDEF. Otherwise, use a libcall for G_CTLZ_ZERO_UNDEF and
lower G_CTLZ in terms of it.

In order to achieve this we need to add support to the LegalizerHelper
for the legalization of G_CTLZ_ZERO_UNDEF for s32 as a libcall (__clzsi2).

We also need to allow lowering of G_CTLZ in terms of G_CTLZ_ZERO_UNDEF
if that is supported as a libcall, as opposed to just if it is Legal or
Custom. Due to a minor refactoring of the helper function in charge of
this, we will also allow the same behaviour for G_CTTZ and G_CTPOP.
This is not going to be a problem in practice since we don't yet have
support for treating G_CTTZ and G_CTPOP as libcalls (not even in
DAGISel).

Reg bank select:
Map G_CTLZ to GPR. G_CTLZ_ZERO_UNDEF should not make it to this point.

Instruction select:
Nothing to do.

llvm-svn: 347545

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[GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

Also bringing ARMRegisterBankInfo::getRegBankFromRegClass
implementation up to speed with the *.td-definition.

Reviewed By: qcolombet

[GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

Also bringing ARMRegisterBankInfo::getRegBankFromRegClass
implementation up to speed with the *.td-definition.

Reviewed By: qcolombet

Differential Revision: https://reviews.llvm.org/D43982

llvm-svn: 333056

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[ARM GlobalISel] Map G_SITOFP and G_UITOFP

Straightforward mapping (integer operand to GPR, floating point operand
to FPR).

llvm-svn: 323731

[ARM GlobalISel] Map G_FPTOSI and G_FPTOUI

Straightforward mapping (integer operand goes to GPR, floating point
operand goes to FPR).

llvm-svn: 323727

[ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR

llvm-svn: 322657

[ARM GlobalISel] Map G_FMA to FPR

llvm-svn: 322367

[ARM GlobalISel] Map G_FNEG to the FPR bank

llvm-svn: 322169

[ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32

Mark conversions between pointers and 32-bit scalars as legal, map them
to the GPR and select to a simple COPY.

llvm-svn: 321356

[ARM GlobalISel] Fix assertion in RegBankSelect

We get an assertion in RegBankSelect for code along the lines of
my_32_bit_int = my_64_bit_int, which tends to translate into a 64-bit
load, followed

[ARM GlobalISel] Fix assertion in RegBankSelect

We get an assertion in RegBankSelect for code along the lines of
my_32_bit_int = my_64_bit_int, which tends to translate into a 64-bit
load, followed by a G_TRUNC, followed by a 32-bit store. This appears in
a couple of places in the test-suite.

At the moment, the legalizer doesn't distinguish between integer and
floating point scalars, so a 64-bit load will be marked as legal for
targets with VFP, and so will the rest of the sequence, leading to a
slightly bizarre G_TRUNC reaching RegBankSelect.

Since the current support for 64-bit integers is rather immature, this
patch works around the issue by explicitly handling this case in
RegBankSelect and InstructionSelect. In the future, we may want to
revisit this decision and make sure 64-bit integer loads are narrowed
before reaching RegBankSelect.

llvm-svn: 321165

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[ARM GlobalISel] Support G_FDIV for s32 and s64

TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.

For the legalizer and reg bank select, we do the same thing as

[ARM GlobalISel] Support G_FDIV for s32 and s64

TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.

For the legalizer and reg bank select, we do the same thing as for the
other floating point binary operations: either mark as legal if we have
a FP unit or lower to a libcall, and map to the floating point
registers.

llvm-svn: 318915

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[ARM GlobalISel] Support G_FMUL for s32 and s64

TableGen already generates code for selecting a G_FMUL, so we only need
to add a test for that part.

For the legalizer and reg bank select, we do the

[ARM GlobalISel] Support G_FMUL for s32 and s64

TableGen already generates code for selecting a G_FMUL, so we only need
to add a test for that part.

For the legalizer and reg bank select, we do the same thing as the other
floating point binary operators: either mark as legal if we have a FP
unit or lower to a libcall, and map to the floating point registers.

llvm-svn: 318910

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Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, n

Fix a bunch more layering of CodeGen headers that are in Target

All these headers already depend on CodeGen headers so moving them into
CodeGen fixes the layering (since CodeGen depends on Target, not the
other way around).

llvm-svn: 318490

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[GlobalISel|ARM] : Allow legalizing G_FSUB

Adding support for VSUB.
Reviewed by: @rovka
Differential Revision: https://reviews.llvm.org/D39261

llvm-svn: 316902

[ARM] GlobalISel: Map shift operands to GPRs

llvm-svn: 315067

[GISEl]: Translate phi into G_PHI

G_PHI has the same semantics as PHI but also has types.
This lets us verify that the types in the G_PHI are consistent.
This also allows specifying legalization act

[GISEl]: Translate phi into G_PHI

G_PHI has the same semantics as PHI but also has types.
This lets us verify that the types in the G_PHI are consistent.
This also allows specifying legalization actions for G_PHIs.

https://reviews.llvm.org/D36990

llvm-svn: 311596

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[GlobalISel] Make GlobalISel a non-optional library.

With this change, the GlobalISel library gets always built. In
particular, this is not possible to opt GlobalISel out of the build
using the LLVM

[GlobalISel] Make GlobalISel a non-optional library.

With this change, the GlobalISel library gets always built. In
particular, this is not possible to opt GlobalISel out of the build
using the LLVM_BUILD_GLOBAL_ISEL variable any more.

llvm-svn: 309990

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[ARM] GlobalISel: Map G_GLOBAL_VALUE to GPR

A G_GLOBAL_VALUE is basically a pointer, so it should live in the GPR.

llvm-svn: 309101

[ARM] GlobalISel: Support G_BRCOND

Insert a TSTri to set the flags and a Bcc to branch based on their
values. This is a bit inefficient in the (common) cases where the
condition for the branch comes

[ARM] GlobalISel: Support G_BRCOND

Insert a TSTri to set the flags and a Bcc to branch based on their
values. This is a bit inefficient in the (common) cases where the
condition for the branch comes from a compare right before the branch,
since we set the flags both as part of the compare lowering and as part
of the branch lowering. We're going to live with that until we settle on
a principled way to handle this kind of situation, which occurs with
other patterns as well (combines might be the way forward here).

llvm-svn: 308009

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[ARM] GlobalISel: Support G_BR

This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is alread

[ARM] GlobalISel: Support G_BR

This boils down to not crashing in reg bank select due to the lack of
register operands on this instruction, and adding some tests. The
instruction selection is already covered by the TableGen'erated code.

llvm-svn: 307904

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Fixup r307893: Silence warning

Silence unused variable warning in release builds.
*sigh*

llvm-svn: 307896

[ARM] GlobalISel: Move local variable. NFC

Move a local variable from outside a switch to inside every case that
needs it (which isn't all of the cases, of course).

llvm-svn: 307893

[ARM] GlobalISel: Add reg mapping for s64 G_FCMP

Map the result into GPR and the operands into FPR.

llvm-svn: 307653

[ARM] GlobalISel: Map s32 G_FCMP in reg bank select

Map hard G_FCMP operands to FPR and the result to GPR.

llvm-svn: 307245

[ARM] GlobalISel: Support G_SELECT for i32

* Mark as legal for (s32, i1, s32, s32)
* Map everything into GPRs
* Select to two instructions: a CMP of the condition against 0, to set
the flags, and

[ARM] GlobalISel: Support G_SELECT for i32

* Mark as legal for (s32, i1, s32, s32)
* Map everything into GPRs
* Select to two instructions: a CMP of the condition against 0, to set
the flags, and a MOVCCr to select between the two inputs based on the
flags that we've just set

llvm-svn: 306382

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[ARM] GlobalISel: Support G_ICMP for i32 and pointers

Add support throughout the pipeline:
- mark as legal for s32 and pointers
- map to GPRs
- lower to a sequence of instructions, which moves 0 or

[ARM] GlobalISel: Support G_ICMP for i32 and pointers

Add support throughout the pipeline:
- mark as legal for s32 and pointers
- map to GPRs
- lower to a sequence of instructions, which moves 0 or 1 into the
result register based on the flags set by a CMPrr

We have copied from FastISel a helper function which maps CmpInst
predicates into ARMCC codes. Ideally, we should be able to move it
somewhere that both FastISel and GlobalISel can use.

llvm-svn: 305672

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