Ok get rid of the REST of the tabs

llvm-svn: 15564

Death to tabs

llvm-svn: 15563

Fix fallout from getOffsetOfLocalArea() being negated. Debugging dumps were being
printed incorrectly, and we were reserving 8 extra bytes of stack space for functions
on X86.

llvm-svn: 14152

Fix the prolog epilog code inserter to match the documentation and support
targets whose stack grows up.

Patch contributed by Vladimir Prus

llvm-svn: 14111

Adjust to new TargetMachine interface

llvm-svn: 13956

Make dense maps keyed on physical registers smallerusing
MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
approp

Make dense maps keyed on physical registers smallerusing
MRegisterInfo::getNumRegs() instead of
MRegisterInfo::FirstVirtualRegister.

Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.

llvm-svn: 11477

show more ...

Allow for fixed objects to reside in the local area, and if they don't to not
clobber them by allocating other objects in the same space!

llvm-svn: 11454

There is no reason to align the stack pointer if there are no callees of this function!

llvm-svn: 11449

Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
Machi

Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340

show more ...

Do not use MachineOperand::isVirtualRegister either!

llvm-svn: 11283

Eliminate users of MachineOperand::isPhysicalRegister

llvm-svn: 11278

Change interface of MachineOperand as follows:

a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits3

Change interface of MachineOperand as follows:

a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

show more ...

Put all LLVM code into the llvm namespace, as per bug 109.

llvm-svn: 9903

Added LLVM project notice to the top of every C++ source file.
Header files will be on the way.

llvm-svn: 9298

Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check

Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}

llvm-svn: 8960

show more ...

Factory methods for FunctionPasses now return type FunctionPass *.

llvm-svn: 7823

(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
from

(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

show more ...

Fix a bug which occurred with empty basic blocks

llvm-svn: 5982

Fix problems with empty basic blocks

llvm-svn: 5326

Arg, fix bugs in previous checkin...

llvm-svn: 5322

Add assertion

llvm-svn: 5321

* Insert prolog/epilog code before rewriting indexes
* Fix calculation of frame offsets when there is an offset.

llvm-svn: 5318

Rename MachineInstrInfo -> TargetInstrInfo

llvm-svn: 5272

Convert to MachineFunctionPass

llvm-svn: 5218

Rename FunctionFrameInfo to MachineFrameInfo

llvm-svn: 5200