The stack alignment is now computed dynamically, just verify it is correct.

llvm-svn: 27380

Always compute max align.

llvm-svn: 24227

Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the

Add the necessary support to the ISel to allow targets to codegen the new
alignment information appropriately. Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack. Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224

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now that we have a reg class to spill with, get this info from the regclass

llvm-svn: 23559

Now that we have getCalleeSaveRegClasses() info, use it to pass the register
class into the spill/reload methods. Targets can now rely on that argument.

llvm-svn: 23556

Change this code ot pass register classes into the stack slot spiller/reloader
code. PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.

llvm-svn: 23536

Fix a bug in my previous patch that was using the wrong iterator. This fixes
Olden/bisort among others.

llvm-svn: 23124

Make this code safe for when loadRegFromStackSlot inserts multiple instructions.

llvm-svn: 23108

When inserting callee-save register reloads, make sure to skip over any
terminator instructions before the 'ret' in case the target has a
multi-instruction return sequence.

llvm-svn: 22041

Tolerate instrs with extra args

llvm-svn: 21982

Remove trailing whitespace

llvm-svn: 21420

Simplify/speedup the PEI by not having to scan for uses of the callee saved
registers. This information is computed directly by the register allocator
now.

llvm-svn: 19795

Speed this up a bit by making ModifiedRegs a vector<char> not vector<bool>

llvm-svn: 19787

Implicitly defined registers can clobber callee saved registers too!
This fixes the return-address-not-being-saved problem in the Alpha backend.

llvm-svn: 19741

Add an assertion that would have made more sense to duraid

llvm-svn: 19704

Put this change back in after testing from Reid proved its innocence. getSpillSize now returns value in bits

llvm-svn: 16102

Back out change to divide getSpillSize by 8 until I figure out why it breaks x86, which has register sizes in bits.

llvm-svn: 16073

Register sizes are in bits, not bytes

llvm-svn: 16070

Register info alignment is in bits, frame object alignment is (currently) in
bytes.

llvm-svn: 15970

Now that we have per-register spill size/alignment info, remove more uses
of getRegClass

llvm-svn: 15967

Stop using CreateStackObject(RegClass*)

llvm-svn: 15775

These methods no longer take a TargetRegisterClass* operand.

llvm-svn: 15774

Make this compile on gc 3.4.1 (static_cast to non-const type was not
allowed).

llvm-svn: 15766

Elminiate MachineFunction& argument from eliminateFrameIndex

llvm-svn: 15736

Split saveCallerSavedRegisters into two methods for clarity, and add comments.
Add support for targets that must spill certain physregs at certain locations.

Patch contributed by Nate Begeman, sligh

Split saveCallerSavedRegisters into two methods for clarity, and add comments.
Add support for targets that must spill certain physregs at certain locations.

Patch contributed by Nate Begeman, slightly hacked by me.

llvm-svn: 15701

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