[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 315380

[PEI] Remove required properties and use 'if' instead of std::function

Summary:
After r303360, we initialize UsesCalleeSaves in runOnMachineFunction,
which runs after getRequiredProperties. UsesCall

[PEI] Remove required properties and use 'if' instead of std::function

Summary:
After r303360, we initialize UsesCalleeSaves in runOnMachineFunction,
which runs after getRequiredProperties. UsesCalleeSaves was initialized
to 'false', so getRequiredProperties would always return an empty set.
We don't have a TargetMachine available early anymore after r303360.
Just removing the requirement of NoVRegs seems to make things work, so
let's do that.

Reviewers: thegameg, dschuff, MatzeB

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D38597

llvm-svn: 315089

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[CodeGen] Emit necessary .note sections for -fsplit-stack

Summary:
According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is

[CodeGen] Emit necessary .note sections for -fsplit-stack

Summary:
According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is used (and also .note.GNU-no-split-stack section if it also contains non-split-stack functions), so it can handle the cases where a split-stack function calls non-split-stack function.

This change adds the sections if needed.

Fixes PR #34670.

Reviewers: thanm, rnk, luqmana

Reviewed By: rnk

Subscribers: llvm-commits

Patch by Cherry Zhang <cherryyz@google.com>

Differential Revision: https://reviews.llvm.org/D38051

llvm-svn: 314335

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Retire the llvm.dbg.mir hack after r311594.

llvm-svn: 311610

Add "Restored" flag to CalleeSavedInfo

The liveness-tracking code assumes that the registers that were saved
in the function's prolog are live outside of the function. Specifically,
that registers t

Add "Restored" flag to CalleeSavedInfo

The liveness-tracking code assumes that the registers that were saved
in the function's prolog are live outside of the function. Specifically,
that registers that were saved are also live-on-exit from the function.
This isn't always the case as illustrated by the LR register on ARM.

Differential Revision: https://reviews.llvm.org/D36160

llvm-svn: 310619

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Remove PrologEpilogInserter's usage of DBG_VALUE's offset field

In the last half-dozen commits to LLVM I removed code that became dead
after removing the offset parameter from llvm.dbg.value gradual

Remove PrologEpilogInserter's usage of DBG_VALUE's offset field

In the last half-dozen commits to LLVM I removed code that became dead
after removing the offset parameter from llvm.dbg.value gradually
proceeding from IR towards the backend. Before I can move on to
DwarfDebug and friends there is one last side-called offset I need to
remove: This patch modifies PrologEpilogInserter's use of the
DBG_VALUE's offset argument to use a DIExpression instead. Because the
PrologEpilogInserter runs at the Machine level I had to play a little
trick with a named llvm.dbg.mir node to get the DIExpressions to print
in MIR dumps (which print the llvm::Module followed by the
MachineFunction dump).

I also had to add rudimentary DwarfExpression support to CodeView and
as a side-effect also fixed a bug (CodeViewDebug::collectVariableInfo
was supposed to give up on variables with complex DIExpressions, but
would fail to do so for fragments, which are also modeled as
DIExpressions).

With this last holdover removed we will have only one canonical way of
representing offsets to debug locations which will simplify the code
in DwarfDebug (and future versions of CodeViewDebug once it starts
handling more complex expressions) and make it easier to reason about.

This patch is NFC-ish: All test case changes are for assembler
comments and the binary output does not change.

rdar://problem/33580047
Differential Revision: https://reviews.llvm.org/D36125

llvm-svn: 309751

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[OptRemark] Allow streaming of 64-bit integers

llvm-svn: 309293

[PEI] Fix refactoring from r308664

llvm-svn: 308666

[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping imp

[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308664

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Revert "[PEI] Simplify handling of targets with no phys regs. NFC"

This reverts commit ce30ab6e5598f3c24f59ad016dc9526bc9a1d450.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizer

Revert "[PEI] Simplify handling of targets with no phys regs. NFC"

This reverts commit ce30ab6e5598f3c24f59ad016dc9526bc9a1d450.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

llvm-svn: 308581

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Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"

This reverts commit 540f6a26ae932469804a379ce9a8cbe715d59c23.

sanitizer-ppc64le-linux seems to segfault when testing

Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"

This reverts commit 540f6a26ae932469804a379ce9a8cbe715d59c23.

sanitizer-ppc64le-linux seems to segfault when testing the sanitizers.

llvm-svn: 308580

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[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping imp

[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308573

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Revert "[PEI] Separate saving and restoring CSRs into different functions. NFC"

This reverts commit a84d1fa6847e70ebf63594d41a00b473c941bd72.

llvm-svn: 308562

[PEI] Add basic opt-remarks support

Add optimization remarks support to the PrologueEpilogueInserter. For
now, emit the stack size as an analysis remark, but more additions wrt
shrink-wrapping may b

[PEI] Add basic opt-remarks support

Add optimization remarks support to the PrologueEpilogueInserter. For
now, emit the stack size as an analysis remark, but more additions wrt
shrink-wrapping may be added.

https://reviews.llvm.org/D35645

llvm-svn: 308556

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[PEI] Simplify handling of targets with no phys regs. NFC

Make doSpillCalleeSavedRegs a member function, instead of passing most
of the members of PEI as arguments.

Differential Revision: https://r

[PEI] Simplify handling of targets with no phys regs. NFC

Make doSpillCalleeSavedRegs a member function, instead of passing most
of the members of PEI as arguments.

Differential Revision: https://reviews.llvm.org/D35642

llvm-svn: 308555

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[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping imp

[PEI] Separate saving and restoring CSRs into different functions. NFC

Split insertCSRSpillsAndRestores into insertCSRSaves + insertCSRRestores.

This is mostly useful for future shrink-wrapping improvements where we
want to save / restore a specific part of the CSRs in a specific block.

Differential Revision: https://reviews.llvm.org/D35644

llvm-svn: 308554

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Revert "r306529 - [X86] Correct dwarf unwind information in function epilogue"

I am 99% sure that this breaks the PPC ASAN build bot:
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds

Revert "r306529 - [X86] Correct dwarf unwind information in function epilogue"

I am 99% sure that this breaks the PPC ASAN build bot:
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/3112/steps/64-bit%20check-asan/logs/stdio

If it doesn't go back to green, we can recommit (and fix the original
commit message at the same time :) ).

llvm-svn: 306676

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[X86] Correct dwarf unwind information in function epilogue

CFI instructions that set appropriate cfa offset and cfa register are now
inserted in emitEpilogue() in X86FrameLowering.

Majority of the

[X86] Correct dwarf unwind information in function epilogue

CFI instructions that set appropriate cfa offset and cfa register are now
inserted in emitEpilogue() in X86FrameLowering.

Majority of the changes in this patch:

1. Ensure that CFI instructions do not affect code generation.
2. Enable maintaining correct information about cfa offset and cfa register
in a function when basic blocks are reordered, merged, split, duplicated.

These changes are target independent and described below.

Changed CFI instructions so that they:

1. are duplicable
2. are not counted as instructions when tail duplicating or tail merging
3. can be compared as equal

Add information to each MachineBasicBlock about cfa offset and cfa register
that are valid at its entry and exit (incoming and outgoing CFI info). Add
support for updating this information when basic blocks are merged, split,
duplicated, created. Add a verification pass (CFIInfoVerifier) that checks
that outgoing cfa offset and register of predecessor blocks match incoming
values of their successors.

Incoming and outgoing CFI information is used by a late pass
(CFIInstrInserter) that corrects CFA calculation rule for a basic block if
needed. That means that additional CFI instructions get inserted at basic
block beginning to correct the rule for calculating CFA. Having CFI
instructions in function epilogue can cause incorrect CFA calculation rule
for some basic blocks. This can happen if, due to basic block reordering,
or the existence of multiple epilogue blocks, some of the blocks have wrong
cfa offset and register values set by the epilogue block above them.

Patch by Violeta Vukobrat.

Differential Revision: https://reviews.llvm.org/D18046

llvm-svn: 306529

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RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFC

These parts do not depend on any PrologEpilogInserter logic and
therefore better fits RegisterScaveging.cpp.

llvm-svn:

RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFC

These parts do not depend on any PrologEpilogInserter logic and
therefore better fits RegisterScaveging.cpp.

llvm-svn: 304596

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AArch64/PEI: Do not add reserved regs to liveins

We do not track liveness for reserved registers. It is unnecessary to
add them to block livein lists.

llvm-svn: 304059

CodeGen: Rename DEBUG_TYPE to match passnames

Rename the DEBUG_TYPE to match the names of corresponding passes where
it makes sense. Also establish the pattern of simply referencing
DEBUG_TYPE inste

CodeGen: Rename DEBUG_TYPE to match passnames

Rename the DEBUG_TYPE to match the names of corresponding passes where
it makes sense. Also establish the pattern of simply referencing
DEBUG_TYPE instead of repeating the passname where possible.

llvm-svn: 303921

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[LegacyPassManager] Remove TargetMachine constructors

This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handli

[LegacyPassManager] Remove TargetMachine constructors

This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
`getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
`addRequired<TargetPassConfig>` and call
`getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

llvm-svn: 303360

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ARM: Compute MaxCallFrame size early

This exposes a method in MachineFrameInfo that calculates
MaxCallFrameSize and calls it after instruction selection in the ARM
target.

This avoids
ARMBaseRegist

ARM: Compute MaxCallFrame size early

This exposes a method in MachineFrameInfo that calculates
MaxCallFrameSize and calls it after instruction selection in the ARM
target.

This avoids
ARMBaseRegisterInfo::canRealignStack()/ARMFrameLowering::hasReservedCallFrame()
giving different answers in early/late phases of codegen.

The testcase shows a particular nasty example result of that where we
would fail to properly align an alloca.

Differential Revision: https://reviews.llvm.org/D32622

llvm-svn: 302303

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PEI: Skip dead objects when looking at CSRs

On AMDGPU if an SGPR is spilled to a VGPR, the frame index
is deleted. If there were any CSR SGPRs, this woudl
assert when setting the offset.

llvm-svn:

PEI: Skip dead objects when looking at CSRs

On AMDGPU if an SGPR is spilled to a VGPR, the frame index
is deleted. If there were any CSR SGPRs, this woudl
assert when setting the offset.

llvm-svn: 301961

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Move size and alignment information of regclass to TargetRegisterInfo

1. RegisterClass::getSize() is split into two functions:
- TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC

Move size and alignment information of regclass to TargetRegisterInfo

1. RegisterClass::getSize() is split into two functions:
- TargetRegisterInfo::getRegSizeInBits(const TargetRegisterClass &RC) const;
- TargetRegisterInfo::getSpillSize(const TargetRegisterClass &RC) const;
2. RegisterClass::getAlignment() is replaced by:
- TargetRegisterInfo::getSpillAlignment(const TargetRegisterClass &RC) const;

This will allow making those values depend on subtarget features in the
future.

Differential Revision: https://reviews.llvm.org/D31783

llvm-svn: 301221

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