Modify the two address instruction pass to remove the duplicate
operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124

When an instruction like: A += B had both A and B virtual registers
spilled, A was loaded from its stack location twice. This fixes the bug.

llvm-svn: 11093

Change interface of MachineOperand as follows:

a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits3

Change interface of MachineOperand as follows:

a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

show more ...

Put all LLVM code into the llvm namespace, as per bug 109.

llvm-svn: 9903

Added LLVM project notice to the top of every C++ source file.
Header files will be on the way.

llvm-svn: 9298

Fixed spelling.

llvm-svn: 8588

Fix assertion in MachineInstr::substituteValue().

llvm-svn: 7675

Do not insert physical regsiters into the regsUsed set

llvm-svn: 7617

All callers of these methods actually wanted them to preserve the flags,
so get rid of the def/use parameters that were getting passed in.

**** This now changes the semantics of these methods to pre

All callers of these methods actually wanted them to preserve the flags,
so get rid of the def/use parameters that were getting passed in.

**** This now changes the semantics of these methods to preserve the flags,
not clobber them!

llvm-svn: 7602

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Simplify code, eliminating the need for the X86 isVoid target instr flag

llvm-svn: 7534

Remove using decl

llvm-svn: 7531

Change interface to MachineInstr::substituteValue to specify more precisely
which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

Allow explicit physical registers for implicit operands.

llvm-svn: 6468

(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
from

(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

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Remove obsolete ctor

llvm-svn: 5301

Rename MachineInstrInfo -> TargetInstrInfo

llvm-svn: 5272

Add support for 3 new forms of MachineOperand

llvm-svn: 5217

* Add printing support for FrameIndex operands

llvm-svn: 5194

Implement printing of MBB arguments

llvm-svn: 5053

Print is const!

llvm-svn: 4737

Remove only uses of markDef/markDefAndUse methods

llvm-svn: 4719

Remove fixme

llvm-svn: 4447

Add special code to make printing SSA form machine instructions nicer

llvm-svn: 4446

Use MRegisterInfo, if available, to print symbolic register names

llvm-svn: 4438

Implement structured machine code printing

llvm-svn: 4435