Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can fee

Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518

show more ...

Rearrange some stuff in MachineOperand and add a new TargetFlags field.

llvm-svn: 74087

Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).

llvm-svn: 74053

Remove some unnecessary #includes.

llvm-svn: 72948

Make DebugLoc independent of DwarfWriter.

-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix ca

Make DebugLoc independent of DwarfWriter.

-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)

llvm-svn: 70520

show more ...

MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.

llvm-svn: 70408

Fix MachineInstr::getNumExplicitOperands to count
variadic operands correctly. Patch by Jakob Stoklund Olesen!

llvm-svn: 69190

Give RemoveRegOperandFromRegInfo a comment and move the
code out of line.

llvm-svn: 69124

ignore register zero in isRegTiedToUseOperand, following the example of
isRegTiedToDefOperand. Thanks to Bob for pointing this out!

llvm-svn: 68734

Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inli

Fix pr3954. The register scavenger asserts for inline assembly with
register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

show more ...

reg0 references are not real registers. This fixes a crash on the
attached testcase.

llvm-svn: 68712

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register al

Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.

llvm-svn: 67512

show more ...

Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.

llvm-svn: 67335

Print out debug info when printing the machine instruction.

llvm-svn: 65067

Add a DebugLoc field and some simple accessors.

llvm-svn: 63152

Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch bu

Use isTerminator() instead of isBranch()||isReturn() in
several places. isTerminator() returns true for a superset
of cases, and includes things like FP_REG_KILL, which are
nither return or branch but aren't safe to move/remat/etc.

llvm-svn: 61373

show more ...

Print subreg information in MachineInstr::dump.

llvm-svn: 61213

Minor code simplification.

llvm-svn: 60804

Drop the reg argument to isRegReDefinedByTwoAddr, which was redundant.

llvm-svn: 60586

Add more const qualifiers. This fixes build breakage from r59540.

llvm-svn: 59542

Make some methods const.

llvm-svn: 59540

Added missing print functions that take a raw_ostream

llvm-svn: 57339

Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006

Fix a think-o in isSafeToMove. This fixes it from thinking that
volatile memory references are safe to move.

llvm-svn: 56948

Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits

Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539

show more ...