History log of /llvm-project/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp (Results 1 – 25 of 40)
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Revision tags: llvmorg-21-init
# 72918fd1 25-Jan-2025 Kazu Hirata <kazu@google.com>

[GlobalISel] Avoid repeated hash lookups (NFC) (#124393)


# 220004d2 23-Jan-2025 Alan Li <me@alanli.org>

[GISel] Add more FP opcodes to CSE (#123949)

Resubmit, previously PR has compilation issues.


# c938436f 22-Jan-2025 Danial Klimkin <dklimkin@google.com>

Revert "[GISel] Add more FP opcodes to CSE (#123624)" (#123954)

This reverts commit 43177b524ee06dfc09cbc357ff277d4f53f5dc15.


# 43177b52 22-Jan-2025 lialan <me@alanli.org>

[GISel] Add more FP opcodes to CSE (#123624)

This fixes #122724


Revision tags: llvmorg-19.1.7, llvmorg-19.1.6
# a35db288 16-Dec-2024 David Green <david.green@arm.com>

[NFC] Remove some unnecessary semicolons

All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.


Revision tags: llvmorg-19.1.5, llvmorg-19.1.4
# 84b7bcfc 30-Oct-2024 Petar Avramovic <Petar.Avramovic@amd.com>

GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)

Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used i

GlobalISel/MachineIRBuilder: Construct DstOp with VRegAttrs (#113581)

Allow construction of DstOp with VRegAttrs.
Also allow construction with register class or bank and LLT.
Intended to be used in lowering code for reg-bank-select where
new registers need to have both register bank and LLT.
Add support for new type of DstOp in CSEMIRBuilder.

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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0
# 0a1aa6cd 14-Sep-2023 Arthur Eubanks <aeubanks@google.com>

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future chang

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

This will make it easy for callers to see issues with and fix up calls
to createTargetMachine after a future change to the params of
TargetMachine.

This matches other nearby enums.

For downstream users, this should be a fairly straightforward
replacement,
e.g. s/CodeGenOpt::Aggressive/CodeGenOptLevel::Aggressive
or s/CGFT_/CodeGenFileType::

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Revision tags: llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3
# 41e71f50 21-Aug-2023 Fangrui Song <i@maskray.me>

[GlobalISel] Remove unneeded empty check. NFC


Revision tags: llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2
# 7021182d 16-Apr-2023 Shraiysh Vaishay <shraiysh@gmail.com>

[nfc][llvm] Replace pointer cast functions in PointerUnion by llvm casting functions.

This patch replaces the uses of PointerUnion.is function by llvm::isa,
PointerUnion.get function by llvm::cast,

[nfc][llvm] Replace pointer cast functions in PointerUnion by llvm casting functions.

This patch replaces the uses of PointerUnion.is function by llvm::isa,
PointerUnion.get function by llvm::cast, and PointerUnion.dyn_cast by
llvm::dyn_cast_if_present. This is according to the FIXME in
the definition of the class PointerUnion.

This patch does not remove them as they are being used in other
subprojects.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D148449

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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4
# 00e55531 02-Mar-2023 Aditya Nandakumar <aditya_nandakumar@adityan.scv.apple.com>

[GISel][CSE][NFC]: Handle mutual recursion when inserting node

GISel's CSE mechanism lazily inserts instructions into the CSE List
to improve on efficiency as well as efficacy of CSE
(for allowing p

[GISel][CSE][NFC]: Handle mutual recursion when inserting node

GISel's CSE mechanism lazily inserts instructions into the CSE List
to improve on efficiency as well as efficacy of CSE
(for allowing partially built instructions to be fully built).

There's unfortunately a mutual recursion via
`handleRecordedInsts -> handleRecordedInst -> insertNode-> handleRecordedInsts`.

So this change simply records that we're already draining this list so we can just bail out on the recursion.

No changes to codegen are expected as we're still draining/handling the temporary
list via pop_back and we should get the same sequence of instructions
whether we call pop_back in a loop at the top level or recursive.

https://reviews.llvm.org/D145006

reviewed by: dsanders

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Revision tags: llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1
# 6ee5a1a0 21-Jul-2020 Matt Arsenault <Matthew.Arsenault@amd.com>

GlobalISel: Enable CSE for G_SEXT_INREG


# 6ee4f253 04-Jan-2023 Diana Picus <Diana-Magda.Picus@amd.com>

[GlobalISel] Add G_BUILD_VECTOR[_TRUNC] to CSE

Add G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC to the list of opcodes in
`shouldCSEOpc`. This simplifies the code generated for vector splats.

Differenti

[GlobalISel] Add G_BUILD_VECTOR[_TRUNC] to CSE

Add G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC to the list of opcodes in
`shouldCSEOpc`. This simplifies the code generated for vector splats.

Differential Revision: https://reviews.llvm.org/D140965

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# 0dc4bdd8 21-Nov-2022 Matt Arsenault <Matthew.Arsenault@amd.com>

GlobalISel: Enable CSE of G_SELECT

Stop trying to delete a select in one combine since it would
be deleting the CSE'd instruction if that happened.


# 9e6d1f4b 17-Jul-2022 Kazu Hirata <kazu@google.com>

[CodeGen] Qualify auto variables in for loops (NFC)


# abda8d22 09-Feb-2022 Jay Foad <jay.foad@amd.com>

[GlobalISel] CSE FP constants at -O0

At -O0 we claim to CSE constants only. I think this should apply to
G_FCONSTANT as well as G_CONSTANT.

Differential Revision: https://reviews.llvm.org/D119344


# 3a8c5148 06-Feb-2022 Kazu Hirata <kazu@google.com>

[CodeGen] Use = default (NFC)

Identified with modernize-use-equals-default


# 14d64be6 01-Jul-2021 Jon Roelofs <jonathan_roelofs@apple.com>

[GISel] Print better error messages for missing Combiner Observer calls

Differential revision: https://reviews.llvm.org/D105290


# ba7a92c0 21-Apr-2021 Nico Weber <thakis@chromium.org>

[Support] Don't include VirtualFileSystem.h in CommandLine.h

CommandLine.h is indirectly included in ~50% of TUs when building
clang, and VirtualFileSystem.h is large.

(Already remarked by jhenders

[Support] Don't include VirtualFileSystem.h in CommandLine.h

CommandLine.h is indirectly included in ~50% of TUs when building
clang, and VirtualFileSystem.h is large.

(Already remarked by jhenderson on D70769.)

No behavior change.

Differential Revision: https://reviews.llvm.org/D100957

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# 905cf88d 13-Feb-2021 Kazu Hirata <kazu@google.com>

[CodeGen] Use range-based for loops (NFC)


# 5c2db165 27-Aug-2020 Aditya Nandakumar <aditya_nandakumar@apple.com>

[GISel]: Fix one more CSE Non determinism

https://reviews.llvm.org/D86676

Sometimes we can have the following code

x:gpr(s32) = G_OP

Say we build G_OP2 to the same x and then delete the previous

[GISel]: Fix one more CSE Non determinism

https://reviews.llvm.org/D86676

Sometimes we can have the following code

x:gpr(s32) = G_OP

Say we build G_OP2 to the same x and then delete the previous instruction. Using something like

Register X = ...;
auto NewMIB = CSEBuilder.buildOp2(X, ... args);

Currently there's a mismatch in how NewMIB is profiled and inserted into the CSEMap (ie it doesn't consider register bank/register class along with type).Unify the profiling by refactoring and calling the common method.

This was found by turning on the CSEInfo::verify in at the end of each of our GISel passes which turns inconsistent state/non determinism in CSEing into crashes which likely usually indicates missing calls to Observer on mutations (the most common case). Here non determinism usually means not cseing sometimes, but almost never about producing incorrect code.
Also this patch adds this verification at the end of the combiners as well.

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# 63c081e7 17-Jul-2020 Aditya Nandakumar <aditya_nandakumar@apple.com>

[GISel: Add support for CSEing SrcOps which are immediates

https://reviews.llvm.org/D84072

Add G_EXTRACT to CSEConfigFull and add unit test as well.


Revision tags: llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2
# 5f7e38d8 08-Jun-2020 Matt Arsenault <Matthew.Arsenault@amd.com>

GlobalISel: Use Register


# f41994f8 08-Jun-2020 Matt Arsenault <Matthew.Arsenault@amd.com>

GlobalISel: Make it clearer that regbank/class are mutually exclusive


Revision tags: llvmorg-10.0.1-rc1
# 3db893b3 23-Apr-2020 Aditya Nandakumar <aditya_nandakumar@apple.com>

[GISel]: Relax opcode checking at the top level to enable CSE

Loosen the restriction on what kinds of opcodes can be CSEd as
targets may want to CSE some generic target specific pseudos.
NFC as far

[GISel]: Relax opcode checking at the top level to enable CSE

Loosen the restriction on what kinds of opcodes can be CSEd as
targets may want to CSE some generic target specific pseudos.
NFC as far as this change is concerned as CSEConfig still pretty much is
a subset of this check.

Differential Revision: https://reviews.llvm.org/D78684

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Revision tags: llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3
# b91d9ec0 18-Feb-2020 Aditya Nandakumar <aditya_nandakumar@apple.com>

[GlobalISel]: Fix some non determinism exposed in CSE due to not notifying observers about mutations + add verification for CSE

https://reviews.llvm.org/D67133

While investigating some non determin

[GlobalISel]: Fix some non determinism exposed in CSE due to not notifying observers about mutations + add verification for CSE

https://reviews.llvm.org/D67133

While investigating some non determinism (CSE doesn't produce wrong
code, it just doesn't CSE some times) in GISel CSE on an out of tree
target, I realized that the core issue was that there were lots of code
that mutates (setReg, setRegClass etc), but doesn't notify observers
(CSE in this case but this could be any other observer). In order to
make the Observer be available in various parts of code and to avoid
having to thread it through various API, the MachineFunction now has the
observer as field. This allows it to be easily used in helper functions
such as constrainOperandRegClass.
Also added some invariant verification method in CSEInfo which can
catch these issues (when CSE is enabled).

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