Add debugging code to the packetizer

llvm-svn: 275455

Apply clang-tidy's misc-static-assert where it makes sense.

Also fold conditions into assert(0) where it makes sense. No functional
change intended.

llvm-svn: 270982

Add DAG mutation interface to the DFA packetizer

llvm-svn: 262930

CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC

In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*. In DFAPacketizer::endPacket(), take
Ma

CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC

In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*. In DFAPacketizer::endPacket(), take
MachineBasicBlock::iterator. Besides cleaning up the API, this is in
search of PR26753.

llvm-svn: 262142

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Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"

This reverts commit r261504, since it's not obvious the new name is
better:
http://lists.llvm.org/pipermail/llvm-commits/Week

Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"

This reverts commit r261504, since it's not obvious the new name is
better:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html

I'll recommit if we get consensus that it's the right direction.

llvm-svn: 261567

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CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC

Delete MachineInstr::getIterator(), since the term "iterator" is
overloaded when talking about MachineInstr.

- Downcast to ilist_node

CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC

Delete MachineInstr::getIterator(), since the term "iterator" is
overloaded when talking about MachineInstr.

- Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so
that ilist_node::getIterator() is still available.
- Add it back as MachineInstr::getInstrIterator(). This matches the
naming in MachineBasicBlock.
- Add MachineInstr::getBundleIterator(). This is explicitly called
"bundle" (not matching MachineBasicBlock) to disintinguish it clearly
from ilist_node::getIterator().
- Update all calls. Some of these I switched to `auto` to remove
boiler-plate, since the new name is clear about the type.

There was one call I updated that looked fishy, but it wasn't clear what
the right answer was. This was in X86FrameLowering::inlineStackProbe(),
added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to
leave the behaviour unchanged, but I'll reply to the original commit on
the list in a moment.

llvm-svn: 261504

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[Packetizer] Code cleanup, NFC

llvm-svn: 257805

[Packetizer] Add a check whether an instruction should be packetized now

Add a function VLIWPacketizerList::shouldAddToPacket, which will allow
specific implementations to decide if it is profitable

[Packetizer] Add a check whether an instruction should be packetized now

Add a function VLIWPacketizerList::shouldAddToPacket, which will allow
specific implementations to decide if it is profitable to add given
instruction to the current packet.

llvm-svn: 255780

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[Packetizer] Add AliasAnalysis as a parameter to the packetizer

This will make the depedence graph more accurate if an alias analysis
is provided. If nullptr is specified in its place, the behavior

[Packetizer] Add AliasAnalysis as a parameter to the packetizer

This will make the depedence graph more accurate if an alias analysis
is provided. If nullptr is specified in its place, the behavior will
remain as it is currently.

llvm-svn: 255540

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Avoid dependency between TableGen and CodeGen

Duplicate a few common definitions between DFAPacketizer.cpp and
DFAPacketizerEmitter.cpp to avoid including files from CodeGen
in TableGen.

llvm-svn:

Avoid dependency between TableGen and CodeGen

Duplicate a few common definitions between DFAPacketizer.cpp and
DFAPacketizerEmitter.cpp to avoid including files from CodeGen
in TableGen.

llvm-svn: 253820

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Hexagon V60/HVX DFA scheduler support

Extended DFA tablegen to:
- added "-debug-only dfa-emitter" support to llvm-tblgen

- defined CVI_PIPE* resources for the V60 vector coprocessor

- allow

Hexagon V60/HVX DFA scheduler support

Extended DFA tablegen to:
- added "-debug-only dfa-emitter" support to llvm-tblgen

- defined CVI_PIPE* resources for the V60 vector coprocessor

- allow specification of multiple required resources
- supports ANDs of ORs
- e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
(SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

- added support for combo resources
- allows specifying ORs of ANDs
- e.g. [CVI_XLSHF, CVI_MPY01] means:
(CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

- increased DFA input size from 32-bit to 64-bit
- allows for a maximum of 4 AND'ed terms of 16 resources

- supported expressions now include:

expression => term [AND term] [AND term] [AND term]
term => resource [OR resource]*
resource => one_resource | combo_resource
combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

Reapply the previous patch, this time without circular dependencies.

llvm-svn: 253793

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Revert r253790: it breaks all builds for some reason.

llvm-svn: 253791

Hexagon V60/HVX DFA scheduler support

Extended DFA tablegen to:
- added "-debug-only dfa-emitter" support to llvm-tblgen

- defined CVI_PIPE* resources for the V60 vector coprocessor

- allow

Hexagon V60/HVX DFA scheduler support

Extended DFA tablegen to:
- added "-debug-only dfa-emitter" support to llvm-tblgen

- defined CVI_PIPE* resources for the V60 vector coprocessor

- allow specification of multiple required resources
- supports ANDs of ORs
- e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means:
(SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1)

- added support for combo resources
- allows specifying ORs of ANDs
- e.g. [CVI_XLSHF, CVI_MPY01] means:
(CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1)

- increased DFA input size from 32-bit to 64-bit
- allows for a maximum of 4 AND'ed terms of 16 resources

- supported expressions now include:

expression => term [AND term] [AND term] [AND term]
term => resource [OR resource]*
resource => one_resource | combo_resource
combo_resource => (one_resource [AND one_resource]*)

Author: Dan Palermo <dpalermo@codeaurora.org>

kparzysz: Verified AMDGPU codegen to be unchanged on all llc
tests, except those dealing with instruction encodings.

llvm-svn: 253790

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ScheduleDAGInstrs: Remove IsPostRA flag; NFC

ScheduleDAGInstrs doesn't behave differently before or after register
allocation. It was only used in a method of MachineSchedulerBase which
behaved diff

ScheduleDAGInstrs: Remove IsPostRA flag; NFC

ScheduleDAGInstrs doesn't behave differently before or after register
allocation. It was only used in a method of MachineSchedulerBase which
behaved differently in MachineScheduler/PostMachineScheduler. Change
this to let MachineScheduler/PostMachineScheduler just pass in a
parameter to that function.

The order of the LiveIntervals* and bool RemoveKillFlags paramters have
been switched to make out-of-tree code fail instead of unintentionally
passing a value intended for the IsPostRA flag to the (previously
following and default initialized) RemoveKillFlags.

Differential Revision: http://reviews.llvm.org/D14245

llvm-svn: 251883

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CodeGen: Remove a few more ilist iterator implicit conversions, NFC

llvm-svn: 249875

Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)

Apparently, the style needs to be agreed upon first.

llvm-svn: 240390

Fixed/added namespace ending comments using clang-tidy. NFC

The patch is generated using this command:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-c

Fixed/added namespace ending comments using clang-tidy. NFC

The patch is generated using this command:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \
llvm/lib/


Thanks to Eugene Kosov for the original patch!

llvm-svn: 240137

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Remove the TargetMachine from DFAPacketizer since it was only
being used to grab subtarget specific things that we can grab
from the MachineFunction anyhow.

llvm-svn: 219650

Remove unused argument to CreateTargetScheduleState and change
the TargetMachine to a TargetSubtargetInfo since everything
we wanted is off of that.

llvm-svn: 219382

Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.

llvm-svn: 216124

Fix null reference creation in ScheduleDAGInstrs constructor call.

Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take refer

Fix null reference creation in ScheduleDAGInstrs constructor call.

Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.

This bug is reported by UBSan.

llvm-svn: 216118

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Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

llvm-svn: 214781

[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.

llvm-svn: 206142

[C++11] Add 'override' keyword to virtual methods that override their base class.

llvm-svn: 203220

mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.

This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn:

mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.

This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn: 189116

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