| #
b8bf3c0f |
| 03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.
Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because Register
Switch AllocationOrder to using RegisterClassInfo instead of a BitVector
of reserved registers.
Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.
llvm-svn: 132581
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Revision tags: llvmorg-2.9.0, llvmorg-2.9.0-rc3, llvmorg-2.9.0-rc2, llvmorg-2.9.0-rc1 |
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| #
2fb5b315 |
| 10-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
llvm-svn: 1
Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.
These functions not longer assert when passed 0, but simply return false instead.
No functional change intended.
llvm-svn: 123155
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| #
4d7432eb |
| 10-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use AllocationOrder in RegAllocGreedy, fix a bug in the hint calculation.
llvm-svn: 121584
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| #
0c67e01e |
| 10-Dec-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an AllocationOrder class that can iterate over the allocatable physical
registers for a given virtual register.
Reserved registers are filtered from the allocation order, and any valid hint is
r
Add an AllocationOrder class that can iterate over the allocatable physical
registers for a given virtual register.
Reserved registers are filtered from the allocation order, and any valid hint is
returned as the first suggestion.
For target dependent hints, a number of arcane target hooks are invoked.
llvm-svn: 121497
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