Add machine operand for MDNodes. This will be used to communicate debug info.

llvm-svn: 74628

Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can fee

Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518

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ad MachineInstrBuilder support for target flags on operands.

llvm-svn: 74155

Rearrange some stuff in MachineOperand and add a new TargetFlags field.

llvm-svn: 74087

fit in 80 cols

llvm-svn: 73838

Give RemoveRegOperandFromRegInfo a comment and move the
code out of line.

llvm-svn: 69124

Comment MO_FPImmediate and doxygenate surrounding comments.

llvm-svn: 61374

Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction s

Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.

llvm-svn: 57748

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Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.

llvm-svn: 57006

Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits

Next round of earlyclobber handling. Approach the
RA problem by expanding the live interval of an
earlyclobber def back one slot. Remove
overlap-earlyclobber throughout. Remove
earlyclobber bits and their handling from
live internals.

llvm-svn: 56539

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explain what earlyclobber actually is.

llvm-svn: 56415

Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a

Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.

llvm-svn: 56290

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adjust last patch per review feedback

llvm-svn: 56194

Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer

Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

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Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode no

Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162

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Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it. No functional change.

llvm-svn: 56161

Use raw_ostream throughout the AsmPrinter.

llvm-svn: 55092

Fix a copy+pasto in an assertion string.

llvm-svn: 53419

Prune and tidy #includes.

llvm-svn: 51697

Back out r48353. Not needed.

llvm-svn: 48375

Add an MO_Undef MachineOperandType, intended for INSERT_SUBREG. Next up MO_Undead.

llvm-svn: 48353

Support a new type of MachineOperand, MO_FPImmediate, used for holding
FP Immediates, crazily enough

llvm-svn: 47117

Add explicit keywords.

llvm-svn: 46506

add efficient iteration support for register use/def's
within a machine function.

llvm-svn: 45479

Implement automatically updated def/use lists for all MachineInstr register
operands. The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.

Implement automatically updated def/use lists for all MachineInstr register
operands. The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.

llvm-svn: 45477

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